# VHDL Flip Flop Syntax Error

I'm trying to figure out how to VHDL, and am having some difficulties writing a simple flip flop. I want a T flip flop that runs strictly off of the clock, changing state every time it receives a rising edge.

The syntax errors are somewhat cryptic and I'm having difficulty figuring out what is wrong.

library lattice;
use lattice.components.all;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

port(
clk     :   IN  STD_LOGIC;
ledout  :   OUT STD_LOGIC
);

signal ledState: STD_LOGIC;
begin
process(clk)
begin
if(rising_edge(clk)) then
--if clk'event and clk='1' then
if ledState = '1' then
ledout <= '0';
elsif ledState = '0' then
ledout <= '1';
endif;
endif;
end process;

ledout <= led_state;

end Behavioral;


I attempted two methods of running on a rising edge, neither seemed to make a difference. This is what the output looks like:

I'm completely lost at this point. What am I doing wrong here?

Thanks!

You have a few issues:

1. endif; should be end if;

2. You already have assignments to ledout within your process, but then you attempt to assign a value to it again in the last line ledout <= led_state;. You can't have multiple drivers for a given signal.

3. Your code is a little over-complicated. You can simplify the toggle of signal ledState like so: ledState <= not ledState; without the embedded if/elsif clause.

4. One of the error messages is pointing out a typo you made in the last line ledout <= led_state;, where I think you meant ledout <= ledState;

library ieee;
use ieee.std_logic_1164.all;

port(
clk     :   IN  std_logic;
ledout  :   OUT std_logic
);

signal ledState: std_logic := '0';
begin
process(clk)
begin
if(rising_edge(clk)) then
ledState <= not ledState;
end if;
end process;

ledout <= ledState;

end Behavioral;


RTL

• Well I guess I'm not following that tutorial anymore. Thanks for pointing those out, it works now. Out of curiosity what did you use to generate the RTL diagram? I'm using Lattice Diamond as my IDE. – alphasierra Oct 20 '17 at 23:23
• @alphasierra Glad I could help. I typically use Xilinx FPGAs. I used Vivado for the RTL diagram. – Blair Fonville Oct 20 '17 at 23:29