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In Quartus Prime (17.0) it take a looong time to generate bitstream on my computer. To generate the rbf for cycloneV, with DDR3 controller and serializer/deserializer in design it take about 12 minutes each time I modify a single parameter in design.

Is there a method to speed the process if design has been already generated in the past ?

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In general, no. Some software packages may support partial synthesis, but this usually requires separate licenses and may require a lot of additional work for partitioning the design. Note that for some parameters (I.e. hard core configuration settings, IOB configuration settings) it may be possible to update the design at a much later point, but this would require manual scripting. I did this with Vivado to change IOB delay values in the bit file without regenerating the entire design, but this a very limited change.

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