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From my limited understanding i feel as though one could just take the synthesis output from Verilog/VHDL code and then use that design to fabricate on silicon the sea of gates.

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  • \$\begingroup\$ An FPGA is technically an ASIC, in that its entire fabric is adaptable to a specific application. \$\endgroup\$ – Matt Young Oct 21 '17 at 15:43
  • \$\begingroup\$ yeah but the FPGA is not an ASIC that someone designs for an ASIC's purpose besides being an FPGA \$\endgroup\$ – spetty flakson Oct 21 '17 at 15:48
  • \$\begingroup\$ @MattYoung And some would say as an FPGA is quite a generic device (it can be used for many applications) that would mean it is not an ASIC. The definition of ASIC is quite vague. I'd call the chips I work on ASICs as these are chips for Radar which is quite specific. At the opposite end an opamp or a chip with logic gates is not an ASIC as it can be used almost anywhere. Anything in the middle depends on your definition of what is an ASIC. \$\endgroup\$ – Bimpelrekkie Oct 21 '17 at 15:50
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    \$\begingroup\$ ASICs have been around ever since we have been making IC's. FPGA have been around since the 80's. During the past 20 to 30 years, the design tools for both have merged and many use VHDL for either. Why use an FPGAs? Reprogramming, quick to market, economical for low volume projects. Why use ASICs? Lower cost for high volume projects. \$\endgroup\$ – st2000 Oct 21 '17 at 15:50
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1) not all ASICs are digital-only. Some have analog circuits as well or are even analog-only.

So your question only applies to digital-only ASICs or only the digital part of an mixed-signal ASIC.

Yes in theory you would think that you could:

1) Write your VHDL

2) Generate the netlist (this describes the actual circuit)

3) Implement that netlist on either FPGA or an ASIC.

But in the real world it is not that simple.

Step 1 is indeed the same but the netlist for an FPGA will be different.

On an FPGA you will only have the gates available which are implemented on that FPGA.

On an ASIC you can choose any gate and as many as you like from the library describing the ASIC's manufacturing process.

This difference means different optimizations might need to be made to either design. For high-speed design it is essential to simulate the netlist so that actual delays are included. This will reveal timing issues that have to be fixed.

So yes, the starting piont (VHDL, Verilog) could be the same but that does not mean you can "blindly" put it on an ASIC or FPGA and expect good results.

What is done in the real world is that first the VHDL or Verilog is evaluated on an FPGA for proper functionality. Then that debugged code is used to make an ASIC. Even then many simulations have to be done to ensure proper functionality.

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  • \$\begingroup\$ Thanks! So in the real world people that design ASICs to start out with FPGAs (and supporting analog circuitry as well? Though i doubt an FPAA is used). \$\endgroup\$ – spetty flakson Oct 21 '17 at 15:49
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    \$\begingroup\$ So in the real world people that design ASICs to start out with FPGAs Not always, it depends on how mature a design is and/or how well it can be simulated and/or how much the designers think testing their design on an FPGA is needed. \$\endgroup\$ – Bimpelrekkie Oct 21 '17 at 15:53
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FPGAs and ASICs have differences e.g. in the reset and initial value behavior. Here is a not complete list. The list could be more specific if you tell us your FPGA vedor and/or the used ASIC library.

FPGAs:

  • general
    • have an power-on reset
    • have an JTAG/debugging interface
  • Flip Flops
    • have asynchronous and synchronous resets
    • have clock enables
    • have a low or high active reset
    • have an init value
  • RAMs
    • have dedicated RAM blocks with fixed sizes
    • have an init value
  • DSPs
    • have arithmetic units for multiplications and addition with fixed sizes

ASICs:

  • general
    • power-on reset needs to be implemented
    • JTAG/debugging needs to be implemented
  • Flip Flops
    • reset, clock enable, ... depends on the primitive library
    • have no init value
  • RAMs
    • are generated by macros
  • DSPs
    • multipliers are generated by macros
    • multiple macros and primitives need to be combined to get the features of a DSP cell
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An FPGA is nothing more than a RAM-based ASIC. While HDL is "portable" from one target to the next, you must always keep in mind what those target libraries offer.

If you prototype an (eventual) ASIC design in an FPGA, you should never use any Hard Macros that the FPGA offers that don't have an "equivalent" in the ASIC library (e.g. IO Tap delays may not be available in your ASIC library whereas they are in Xilinx). Your FPGA should have very distinct boundaries ("Black Box" capabilities) for clocks and resets, memories, and an IO ring, that you can easily swap out when targeting the ASIC.

Typically though, your HDL should translate easily FPGA to ASIC. I highly recommend drawing your design in a program like Visio to show gates, FFs, FSMs, etc. before writing anything. And to help ensure you get what you planned, try not to get "fancy" with your RTL... IMO, being explicit as possible is good practice, even if it does take a few more lines of code.

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  • \$\begingroup\$ Some FPGA's do not have RAM and are fused \$\endgroup\$ – Voltage Spike Apr 26 '18 at 19:03
  • \$\begingroup\$ ^truth... but, in-general, conceptually, and to help alleviate the misnomer that an FPGA consists of "firmware", I prefer to present it as such to help place focus back on the digital IC design and not the target. But, I do appreciate your comment for accuracy-sake. \$\endgroup\$ – CapnJJ Apr 26 '18 at 19:08
  • \$\begingroup\$ Also, some have ROM's (like altera max10, has two sections for two separate configurations) that you can load multiple "firmwares" on the same device's RAM \$\endgroup\$ – Voltage Spike Apr 26 '18 at 19:57

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