From my limited understanding i feel as though one could just take the synthesis output from Verilog/VHDL code and then use that design to fabricate on silicon the sea of gates.
1) not all ASICs are digital-only. Some have analog circuits as well or are even analog-only.
So your question only applies to digital-only ASICs or only the digital part of an mixed-signal ASIC.
Yes in theory you would think that you could:
1) Write your VHDL
2) Generate the netlist (this describes the actual circuit)
3) Implement that netlist on either FPGA or an ASIC.
But in the real world it is not that simple.
Step 1 is indeed the same but the netlist for an FPGA will be different.
On an FPGA you will only have the gates available which are implemented on that FPGA.
On an ASIC you can choose any gate and as many as you like from the library describing the ASIC's manufacturing process.
This difference means different optimizations might need to be made to either design. For high-speed design it is essential to simulate the netlist so that actual delays are included. This will reveal timing issues that have to be fixed.
So yes, the starting piont (VHDL, Verilog) could be the same but that does not mean you can "blindly" put it on an ASIC or FPGA and expect good results.
What is done in the real world is that first the VHDL or Verilog is evaluated on an FPGA for proper functionality. Then that debugged code is used to make an ASIC. Even then many simulations have to be done to ensure proper functionality.
FPGAs and ASICs have differences e.g. in the reset and initial value behavior. Here is a not complete list. The list could be more specific if you tell us your FPGA vedor and/or the used ASIC library.
- have an power-on reset
- have an JTAG/debugging interface
- Flip Flops
- have asynchronous and synchronous resets
- have clock enables
- have a low or high active reset
- have an init value
- have dedicated RAM blocks with fixed sizes
- have an init value
- have arithmetic units for multiplications and addition with fixed sizes
- power-on reset needs to be implemented
- JTAG/debugging needs to be implemented
- Flip Flops
- reset, clock enable, ... depends on the primitive library
- have no init value
- are generated by macros
- multipliers are generated by macros
- multiple macros and primitives need to be combined to get the features of a DSP cell
An FPGA is nothing more than a RAM-based ASIC. While HDL is "portable" from one target to the next, you must always keep in mind what those target libraries offer.
If you prototype an (eventual) ASIC design in an FPGA, you should never use any Hard Macros that the FPGA offers that don't have an "equivalent" in the ASIC library (e.g. IO Tap delays may not be available in your ASIC library whereas they are in Xilinx). Your FPGA should have very distinct boundaries ("Black Box" capabilities) for clocks and resets, memories, and an IO ring, that you can easily swap out when targeting the ASIC.
Typically though, your HDL should translate easily FPGA to ASIC. I highly recommend drawing your design in a program like Visio to show gates, FFs, FSMs, etc. before writing anything. And to help ensure you get what you planned, try not to get "fancy" with your RTL... IMO, being explicit as possible is good practice, even if it does take a few more lines of code.