# Writing SDC constraints for asynchronous clocks

I am new to SDC constraints, in synchronous clock definition say A and B are synchronous with each other, then we can define create_clock on A port (input) and generated_clock on B (output) with divide_by option.

Now say X is input and Y is output, and both are asynchronous with each other. Where such scenario will come in design and how to write SDC constraints on both input and output?

• X and Y are clock ports too, right?
– user154136
Oct 23 '17 at 11:47
• Yes, You can assume anything. I just want to know different scenarios and how to define clock on them Oct 23 '17 at 11:51

The most common way to define clocks synchronous or asynchronous to each other is the set_clock_groups command. The create_generated_clock command is not mandatory to make the clocks synchronous.

If clock A and B are defined as follows, my synthesis and STA tools classify them synchronous, but I don't rely on that and I explicitly define my clock groups.

create_clock           -name CLK_A -period 10 -waveform "0 5" [get_ports A]
create_generated_clock -name CLK_B -source CLK_A -divide_by 2 [get_ports B]


The clocks listed after the same -group switch become synchronous. Please note that CLK_A and CLK_B will also be asynchronous to any other clock (X and Y in this case).

set_clock_groups -asynchronous -group {CLK_A CLK_B}


Let's assume that clock X and Y have the following constraints.

create_clock -name CLK_X -period 20 -waveform "0 10" [get_ports X]
create_clock -name CLK_Y -period 15 -waveform "5 10" [get_ports Y]


If we put them into different groups, they become asynchronous.

set_clock_groups -asynchronous -group CLK_X -group CLK_Y


Now we have 3 clock groups in total. We could also define them with a single command as follows.

set_clock_groups -asynchronous -group {CLK_A CLK_B} -group CLK_X -group CLK_Y