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I'm trying to make DC load up to 20A with 1mA precision.
Current sense resistor is 5mΩ, so the voltage on this current sense will be from 5μV to 100mV. I picked LTC2050HV (datasheet) which have very low input offset (±0.5μV).

This is my circuit:
enter image description here First opamp (U4) just multiplies voltage on current sense (R21) by factor of 40, so Vout1 can be from 0.2mV to 4V. Second opamp (U2) compares this with voltage set by potentiometer (RV1) (it will be replaced DAC later) and controls power mosfet (Q6). There is only one power mosfet IRF540N, I am about to add more parallel mosfets later. This is just a testing circuit.

Problem is that there are some oscillations and I'm not able to remove it.
I tried this this circuit with and without capacitors C1, C6, C12. It had impact on shape and magnitude of oscillations, but it is still there. What I am doing wrong? Or how to improve the stability?
My intention is to stabilize current flowing through current sense, and voltage Vout1 which I will push to 16bit ADC.

I tested my circuit with 500mA load. Control voltage (by RV1 potentiometer) is set to 100mV, so load current is 500mA.

C1 and C12 removed, C6 in circuit.
Vshunt: enter image description here Vout1:
enter image description here

C6 removed, C1 and C12 in circuit.
Vshunt:
enter image description here Vout1:
enter image description here

C6 and C12 removed, C1 in circuit.
Vshunt:
enter image description here Vout1:
enter image description here

So, the best result I get by removing C6 and C12, and keeping C1 in circuit. But Vout1 is still unstable. How to improve it? I would need it under 0.2mV.

Layout:
enter image description here enter image description here enter image description here

UPDATE:
My goal is 0.5% accuracy. That is why I picked this opamp.
So measure 1mA is really 1mA. Measured 20A could be between 19.9A and 20.1A.

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  • \$\begingroup\$ A few things to think about: how clean is your input voltage? How are you measuring (i.e. low [GND] inductance). Have you had a look at the noise figures of your parts? As this is relatively simple, have you tried simulating it and/or compute the phase margins? \$\endgroup\$ – PlasmaHH Oct 23 '17 at 13:41
  • \$\begingroup\$ Try moving the integrator (C12) from the sense side amplifier to the drive side amplifier. \$\endgroup\$ – Peter Smith Oct 23 '17 at 13:44
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    \$\begingroup\$ Even without C1, R30 forms a low pass filter with the gate capacitance, adding phase shift. It should not be 1k. Maybe 10 ohms max. \$\endgroup\$ – τεκ Oct 23 '17 at 14:50
  • \$\begingroup\$ @PlasmaHH noise on input voltage which powers load is 6mVp-p. Noise of +5V and -5V is about 0.3mVp-p. I did not measure inductance of GND. When talking about GND, I made star-ground topology (near one end of current sense). LTC2050HV has 1.5uVp-p noise. I have no experience with calculating phase margins. But I'm eager to learn. Can you recommend me where to start? \$\endgroup\$ – Chupacabras Oct 23 '17 at 15:17
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    \$\begingroup\$ @Chupacabras R30. The gate resistor. \$\endgroup\$ – τεκ Oct 23 '17 at 19:53
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Besides the good PCB layout feedback (NPI) by George Herold:

You have a dominant pole compensated op-amp running open loop in your design. You have an additional pole added to the response with R30 anc C1, or if C1 isn't installed with the gate capacitance of the FET. If this pole is inside the open-loop bandwidth of U2 it will add phase shift and cause your whole loop to be unstable.

From the open loop gain/phase plot it looks like this amplifier has 50 degrees of phase margin and crosses 0dB at 2MHz. Therefore a pole at 2MHz will degrade the phase margin to 5 degrees (45 degrees phase shift at the corner) and anything much lower will make an oscillator.

Unfortunately eliminating R30 may be a problem as well, as these amplifiers probably don't drive pure capacitive loads very well.

The answer is to provide some phase lead compensation in your loop to try to cancel the additional pole you're adding.

You could try closing the loop around U2, if you can add a network that gives you some phase lead you can achieve stability. You might sacrifice some open-loop gain and accuracy that way.

Bottom line is that you have to analyze your loop vs. performance requirements and make sure it has adequate phase margin for the job.

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  • \$\begingroup\$ Ltc2050 indeed does NOT like capacitive loads. \$\endgroup\$ – JRE Oct 23 '17 at 19:15
  • \$\begingroup\$ There is no open loop. U2 has negative feedback through Q6 and U4. \$\endgroup\$ – Chupacabras Nov 15 '17 at 7:53
  • \$\begingroup\$ @Chupacabras Right, what I meant to say was U2 has no LOCAL feedback and therefore adds a low frequency pole and 90 degrees of phase shift to the OUTER feedback loop around it. Then any additional pole within the bandwidth of the loop can add up to 90 degrees of additional phase shift causing instability or low phase margin. This design potentially has multiple additional poles. \$\endgroup\$ – John D Nov 15 '17 at 15:31
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Seriously 1mA precision on 20A? Good luck with that.

Where are the traces with no caps in place?

However, your PCB does not seem to match the schematic... with C2 across the load.

PCB is nasty in general, note how far the gate trace has to run and how it runs parallel to that bit fat 10A trace...

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  • \$\begingroup\$ C2 is just not populated. It's just a residue of my experiments. The layout matches reality and schematic, just ignore that C2 (sorry for confusion). I wanted to keep those opamps away from the heat. Is it better to place it closer to power mosfet? That means it will be farther away from the shunt. I make small steps. I'm not going to draw 10A through this circuit. I am solving those oscillations at this point. \$\endgroup\$ – Chupacabras Oct 23 '17 at 14:49
  • \$\begingroup\$ I have updated those images of layout. C2 removed. \$\endgroup\$ – Chupacabras Oct 23 '17 at 15:05
  • \$\begingroup\$ @Chupacabras the longer the traces the more the parasitic inductance and capacitances and the more open you are to oscillations. Keep things tight. \$\endgroup\$ – Trevor_G Oct 23 '17 at 15:15
  • \$\begingroup\$ @Chupacabras and just dumping in extra capacitances to remove perceived noise is going to get you into this kind of trouble. You need to be more delicate with filters and chose smaller values wisely. The traces you show are what I would expect with those sledgehammers you chose. That's why showing the original traces is more important in this question. \$\endgroup\$ – Trevor_G Oct 23 '17 at 15:19
  • \$\begingroup\$ I know that layout is important, that's why I added it to my question. I realize that layout should correspond to schematics. It does. But I admit that I should remove that C2 not to confuse people. \$\endgroup\$ – Chupacabras Oct 23 '17 at 16:15
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As far as I can tell you have no negative feedback on the second oapmp. The one driving the FET. Try some! And then roll off the gain of the second opamp with a bit of capacitance in parallel with feedback R.

After a little thought, feedback is coming from the other opamp, still try rolling off the gain of the FET driving opamp with some capacitance, from output to inverting input. ~100pF is often a good first guess, if you're a hack and try guy like me... or spice it.

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I did AC analysis according to question/answer here: AC analysis of opamp loop in LTspice

I completely stabilized that loop by these changes:

  1. removed C1
  2. decreased value of R30 to 10Ω
  3. removed C6

Oscillations are gone.

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