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There were a number of questions/answers here somewhat related to this question, but not exactly the same. I am developing an inverter with half bridge MOSFETs with high voltage and current over 100 amperes using parallel MOSFETs.

MOSFETs drains are connected to the copper power bus which will mount outside of the PCB. All the components are undoubtedly part of the same schematic as some of the MOSFETs pins are placed on PCB traces, but a chunk of circuits will be outside of the PCB.

This is a common task for motor controllers and for power supplies, but I can't find guidelines on PCB design. Whatever PCB CAD software is used, the rule check will fail in unconnected parts of the schematic. Please share your experience.

Note: I am using DipTrace for schematic and PCB design, but the workflow should be similar for any CAD to fully use capabilities of CAD and yet escape DRC errors.

This picture shows that two pins will be placed on PCB while Drain "D" is outside on the rail

This portion of schematic shows 'V Battery" power rail which connects to MOSFET drain outside of PCB, yet the same line connects to a resistor, diode and capacitor on the PCB

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I see a few potential approaches

  1. Draw the connections that are on the schematic but not the PCB as "lines" rather than "wires". Preferablly in a different colour so you can quickly see them for manual checking.
  2. Just treat the list of design rule violations as warnings rather than errors. I don't like this approach though because it can be hard to spot the real error in amongst the list of errors you are deliberately ignoring.
  3. Set conditions on the "un-routed net" design rule that exclude particular nets.
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  • \$\begingroup\$ Very good list of options, but a subject to the sophistication of CAD software. 1 - only good if there are no connections to be checked by ERC, otherwise loosing important CAD feature, 2 - I am favoring this ... my DipTrace has a feature localizing the error from the generated list allowing to quickly see what it is about , 3 - DRC rules in DipTrace don't allow me to exclude particular nets from the rule, but I realize if some CAD allow this - this is probably the best solution. \$\endgroup\$ – VladBlanshey Oct 23 '17 at 23:55
  • \$\begingroup\$ I find ERC of very limited usefulness. Lots of false positives, few if any real errors found. \$\endgroup\$ – Peter Green Oct 24 '17 at 1:32
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For off-board components I use a suitable footprint (connector or group of pads) to provide the connection points, and use that footprint name in the schematic, rather than the actual component footprint. This substitute footprint need not match the component pin layout, as long as the footprint pin numbers match the schematic symbol pin numbers.

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  • \$\begingroup\$ As I indicated this is not "off-board" component - it is partially on-board. I added picture of a popular typical MOSFET which is used in this manner... 2pins on-board, drain is off. \$\endgroup\$ – VladBlanshey Oct 23 '17 at 20:51
  • \$\begingroup\$ also this wire-rail is connected to the low current components on board (resistors, diodes and caps) but the high current connection over MOSFET drain tab is only through rail outside of PCB \$\endgroup\$ – VladBlanshey Oct 23 '17 at 20:53
  • \$\begingroup\$ What Peter suggested is that you should create a package with the specific way you are connecting it "half" off-board. \$\endgroup\$ – Wesley Lee Oct 23 '17 at 20:55
  • \$\begingroup\$ in terms of a footprint - I can use true footprint of the MOSFET's two pins which are truly connected to the PCB as per user manual, but the schematic part I don't understand... I added a fragment of schematic where a drain tab of MOSFET shown will be off-board \$\endgroup\$ – VladBlanshey Oct 23 '17 at 21:12
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Typically I create a schematic symbol which represents a MOSFET and a connector as a single unit (2 or 3 pins depending on whether you need a drain connection to the PCB) and then make a PCB symbol that just represents the connector. This passes all the DRC rules.

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  • \$\begingroup\$ can you please clarify: I understand the PCB part - only 2 pins will be matched by pads on board but how to show MOSFET in it's entirety including drain connected to the power line? Power line is still there - it will connect to low current components over PCB too but over rail-only to the drain of the MOSFET \$\endgroup\$ – VladBlanshey Oct 23 '17 at 21:00
  • \$\begingroup\$ You don't in that case. In Diptrace I don't believe there is any way to create an unrouted net in the schematic that will be ignored when generating the netlist for the board and performing the DRC. \$\endgroup\$ – Dean Franks Oct 23 '17 at 22:12
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In my experience, there are times when the DRC can be carefully disregarded. For example, I sometimes have designs where I need a particular component pad to go right to (or even off of) the edge of the PCB, but I don't want to disable that particular design rule, because I want it to flag any other components that I have inadvertently placed too close to an edge.

So in my case, I would design the board, run the DRC and then make sure I was okay with any violations it uncovers, and not worry about it after that.

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  • \$\begingroup\$ thank you for a confirmation - I was also thinking about this - assuming that my CAD software (DipTrace) will allow me to finish design up to generating gerber files (?), then analyzing DRC errors I can figure out which ones belong to the rail ... this could be a simple "solution" even though erroneous :) \$\endgroup\$ – VladBlanshey Oct 23 '17 at 21:17
  • \$\begingroup\$ You can normally consider DRC and ERC (schematic) error messages as warnings to the user. They should not prevent you from creating the Gerber and NC drill files needed to make the PC board. Although it is desirable to clear all error messages, it is sometimes necessary to ignore some, if you are really sure the warning can be ignored. \$\endgroup\$ – Peter Bennett Oct 23 '17 at 21:42
  • \$\begingroup\$ Indeed Peter, it seems that this is the simplest solution to ignore the error messages for high current rail-bus connections and at the same time schematic looks true and easy readable and PCB is true to connections which run through it... in fact this approach can be easy for any problems with partial or even a complete "off-bard" component connection! BTW: only DRC errors will be generated this way, ERC should be fine. \$\endgroup\$ – VladBlanshey Oct 23 '17 at 22:13

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