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Suppose I have a high speed digital signal (represented as a square wave) that splits off and is shared between two subsequent inputs stages (represented as MOSFETs).

Is it better to have two series termination resistors for each input stage?

schematic

simulate this circuit – Schematic created using CircuitLab

Or better to have a single resistor for both stages?

schematic

simulate this circuit

My hunch tells me the former would work best, but the latter could work as long as the post resistor line is routed correctly and kept short. The Internet doesn't seem to have much to say on the matter.

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    \$\begingroup\$ those aren't 'terminating' resistors, they are resistors though. \$\endgroup\$ – Neil_UK Oct 23 '17 at 19:43
  • \$\begingroup\$ I should have said "series termination resistors". I'll fix the question. \$\endgroup\$ – TRISAbits Oct 23 '17 at 19:46
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    \$\begingroup\$ These still aren't termination resistors but current limiting resistors. You should spend one per transistor. \$\endgroup\$ – Janka Oct 23 '17 at 19:52
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I'll assume that your 240MHz source is far enough from your "inputs stages" that you actually have a transmission line and that is why you are asking about termination. If the connection is short you're dealing with a RLC circuit and your resistor is more about damping than termination (more on how to determine if your line is short or long in this question).

If you are dealing with a transmission line then you want to match your 240MHz source to the line. So I would place a single series resistor at the source. This will serve as your source terminator for any reflections coming back. Now let's say you now have a 50 Ohm line after your resistor, if you split it into two 50 Ohm lines well now you have an impedance mismatch? Instead you can split it into two 100 Ohm lines. This is the recommended approach for "bifurcated lines" in Johnson's high speed digital design book.

If you could handle the voltage loss you could go further and end terminate the line at your "inputs stages" and you should have a nice clean setup.

On the other hand your example uses a clock. If all you need to do is get a clock to multiple locations cleanly there are a number of inexpensive clock buffer chips or oscillators themselves that come with 2,4,x outputs. Sometimes it's just easier to use one of those.

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It really depends on the line lengths.

If the line is long between your signal generator and the two inputs, and the latter are close together you need to terminate the line with an impedance that includes both input capacitances and a single resistor.

If the line splits and goes some distance to the two loads, you should, in reality, split the signal properly into two, propagate each, and terminate at each gate.

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I can think only of reasons why the latter is worse than the former:

  1. In the latter case, capacitance from the gates to ground is now in parallel, effectively doubling the input capacitance of the branch.

  2. If the current draw through the gates of one of the FETs was greater than the other, this only causes the gate voltage to drop for that one transistor in the former case. However, in the latter this voltage drop would effect the second as well.

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  • \$\begingroup\$ well, assuming both lines have the same wave impedance, then he'll now needs to match that modified impedance to the feed line, which can at least partially be done resistively. \$\endgroup\$ – Marcus Müller Oct 23 '17 at 20:46

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