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Referring to the following schematic:

cascode stage

My current understanding dictates that a transistor will output a certain drain current given an input voltage at the gate (V1 and V2). How can this behavior stand true in the schematic shown, since there will be two "competing" current sources? Which transistor sets the current of the circuit?

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  • \$\begingroup\$ The PMOS is always the source, and the NMOS is always the sink. \$\endgroup\$ – Ignacio Vazquez-Abrams Oct 23 '17 at 23:24
  • \$\begingroup\$ Disregarding the terminology of "source" vs "sink", both are supposed to individually set a current based on their gate voltages. If these set output currents conflict, which will set the current? \$\endgroup\$ – Sam D20 Oct 23 '17 at 23:28
  • \$\begingroup\$ Whichever one is stronger. You know, KCL and all. \$\endgroup\$ – Ignacio Vazquez-Abrams Oct 23 '17 at 23:29
  • \$\begingroup\$ As long as the FET is in saturation (VGS>Vth, VDS>VGS) the drain current is almost independent of VDS. So if the characteristics of the two are the same, the one with higher VGS-Vth (aka overdrive voltage) will have lower VDS. \$\endgroup\$ – τεκ Oct 24 '17 at 2:16
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Which transistor sets the current of the circuit?

The transistor which tries to make the lowest current.

For a transistor to determine its drain current it must be in saturation mode. For this to happen, Vds > Vgs - Vt so there must be enough Vds and not too much Vgs. If Vgs is too large, the transistor will be in linear mode and behave as a resistor.

Suppose that both NMOS and PMOS have enough Vds to be in saturation, for example when Vout = Vdd/2. Suppose the NMOS wants to make 100 uA flow but the PMOS wants 200 uA to flow. Which one will win?

So there's 200 uA pulling "up" and 100 uA pulling "down" then what does the voltage on Vout do? It will go up as 200 uA pulling up - 100 uA pulling down leaves a net result of 100 uA pulling up.

So the voltage on Vout will go up. What does this mean for the transistors? For the NMOS this is good news, Vds will increase so it can continue to make 100 uA flow. No problem!

For the PMOS things are different, as Vout goes up its Vds will decrease to the point where the PMOS will go out of saturation mode and enter linear mode. The PMOS will have no control over the current. It wants to make 200 uA flow but the NMOS prevents that by taking all the voltage. So the NMOS wins since it wanted the lowest current.

Also if you switch a transistor off by making Vgs = 0 then that transistor will win as there's nothing the other transistor can do to make any current flow.

Realize that it is easy to make less current flow (just drop voltage) but it is impossible to make more current flow than the current a transistor gets from elsewhere.

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  • \$\begingroup\$ Excellent response. This can also be seen by fixing the gate voltage of one of the transistors and doing load line analysis (in this case, its more of a load curve). In doing so, I was able to understand the mathematics behind this, but was not understanding the behavior of the circuit at a higher level. This cleared everything up for me. Thank you! \$\endgroup\$ – Sam D20 Oct 24 '17 at 23:11
  • \$\begingroup\$ Indeed, you can make this more illustrative using a load line analysis. The comments above were a bit "meh" (some even wrong) so I felt compelled to write a proper answer ;-) Glad it helped! \$\endgroup\$ – Bimpelrekkie Oct 25 '17 at 7:44

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