I am not sure if this questions belongs to this stack exchange site but I didn't find other better one. In case it doesn't, let me know and I will move it to some other place.
I am working with a QorIQ T2080 Soc and DDR3L (DDR3-1866 mode, cycle time: 1.071ns @ CL=13 ) memory (model MT41K256M16). The configuration of the DDR3L allows me 1866M/T Data Rate with a 64bits bus-width, so, the theoretical peak achievable data-rate would be 14.9GB/s (1866Mhz * 64bits/8). However, performing a DMA memory copy test, the data-transfer-rate that I obtain is about 4GB/s (2GB/s x 2 because I am copying memory).
I would like to understand where this value comes from.
From what I know, correct me if I am wrong, DMAs normally create the data path when moving memory, and so, data doesn't go through them. Therefore, I didn't consider it as a data-rate limiting factor.
I reached the conclusion that the memory could be the limiting factor and made the following supposition:
The datasheet specify a burst length of 8 transactions of the bus size (64b). It is also specified a CAS latency of 13 for each column access to the memory (cycle time of 1.07ns). As I said before, the maximum peak achievable data-rate should be 14.9GB/s. However, each time we access a new column from the ram, data will only be received during 8 cycles at a frequency of 1866Mhz and then we will have to wait the true latency [3]: CL * 1.07 = 13.9 ns . Hence, I obtain a theoretical worst case:
$$ \frac{64B \: transferred \; in \; a \; burst }{\frac{8 \: burst \; length}{1.866 \: Ghz}+14ns}= 3.4 \; GB/s$$
In [1] they mention that commonly the DDR controller is able to obtain a higher throughput, getting even close to the peak data-rate.
My question is: Is this supposition right?
Other sources where I looked: