I'm using two Xilinx FPGAs (one Kintex 7 and one Artix 7). The Kintex 7 is tied to its own system (OPAL-RT software, it is a simulation software that is an addon to Simulink which lets data be output to an FPGA via a user CPU input) and will be outputting the its data as 10 serial bits.
The problem I am trying to solve is to send 20 serial bits (actually, 16 bits, but when it's encoded it should be 20, if I'm not mistaken) from the Kintex 7 to the Artix 7.
They will be clocked differently, but I thought the point of 8b10b was so that the clock of the primary FPGA can be recovered by the secondary via the data stream.
Clearly I'm not very learned on the subject of setting up a communication link between two Xilinx FPGAs, but if someone has any insight that can help me, it would be super appreciated.
Worth noting is that I have access to Vivado/Xilinx System Generator.