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I'm using two Xilinx FPGAs (one Kintex 7 and one Artix 7). The Kintex 7 is tied to its own system (OPAL-RT software, it is a simulation software that is an addon to Simulink which lets data be output to an FPGA via a user CPU input) and will be outputting the its data as 10 serial bits.

The problem I am trying to solve is to send 20 serial bits (actually, 16 bits, but when it's encoded it should be 20, if I'm not mistaken) from the Kintex 7 to the Artix 7.

They will be clocked differently, but I thought the point of 8b10b was so that the clock of the primary FPGA can be recovered by the secondary via the data stream.

Clearly I'm not very learned on the subject of setting up a communication link between two Xilinx FPGAs, but if someone has any insight that can help me, it would be super appreciated.

Worth noting is that I have access to Vivado/Xilinx System Generator.

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You need a "clock data recovery" (CDR) circuit. Your FPGA may include one as a hard core, if you are using signal rates in the gigabit-per-second range.

This function generally requires some specialized parts, such as a voltage-controlled oscillator (VCO) and an analog control circuit for the VCO, that aren't easily implemented in the FPGA fabric. So if you want to work at frequencies where the FPGA's hard cores don't work, you would need to purchase an external IC to do this function. You'd need to choose a data rate that is used commonly enough to make it worth building ICs to work there.

If you want to send this data at a relatively slow rate (say, below 50 Mb/s), you might want to use Manchester encoding instead of 8b/10b. With Manchester encoding, you can recover the clock from the data using a simple circuit requiring only a couple of gates, without needing a VCO or PLL. Your synthesis tool might not be happy about implementing this circuit, but at low data rates it should work just fine.

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  • \$\begingroup\$ Thanks for the comment, @The_Photon. I think using Manchester coding seems like the way to go in this case. What I would like to do is send at least 12 bits at time (since I have 12 MOSFET gates to control independently) and have the secondary FPGA decode these incoming 12 bits (in order) and send them properly. You think Manchester coding would work? We're working at switching frequencies of ~4kHz, so I think Manchester could work very well. \$\endgroup\$ – Lerbi Oct 24 '17 at 22:10
  • \$\begingroup\$ @Lerbi, yes, for 4 kbps, I would just use Manchester code. If you use 8b10b and a CDR you need to send some kind of signal continuously to keep the CDR locked. There is an "idle" word defined in 8b10b for this purpose. With Manchester you wouldn't need to send idles continuously but you might want to include some kind of start and stop bit framing so the receiver knows when a transmission starts and stops. \$\endgroup\$ – The Photon Oct 24 '17 at 22:40
  • \$\begingroup\$ Thanks a lot, @The_Photon. I'm starting to see some light at the end of the tunnel concerning the project. With Manchester code, there seems to be a clock on the secondary FPGA. Is this necessary? Is there no way to have the FPGA just on its own, along with Vdd and GND, and have the incoming single supply both the clock and the data? \$\endgroup\$ – Lerbi Oct 25 '17 at 4:06
  • \$\begingroup\$ @Lerbi, in FGPA design you will need to get the incoming data onto the clock domain of your internal circuit somehow anyway. \$\endgroup\$ – The Photon Oct 25 '17 at 5:01
  • \$\begingroup\$ Sorry, I hate to bother you further, but can you elaborate on what you mean? \$\endgroup\$ – Lerbi Oct 25 '17 at 14:35

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