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Edit: Added gating signal waveforms. Changed some of the graphs, I accidentally put a test circuit waveforms the first time. Current is not that high but offset is there and current is high for a lower inductance.

I am new to using PLECS and power electronics in general. I am trying to simulate a grid-tied power inverter where I am using a 300V dc power source, inverting it to 60Hz AC, and then connecting to a 60Hz AC grid (120 Vrms).

It successfully gives me the voltage I want. But I am getting a 0.567A dc current offset. This offset and the total current gets very high if I reduce the inductor size. Questions:

  1. Why is there a DC current offset, even across the transformer?
  2. How to reduce this offset to zero?
  3. The power output is awfully high. How to reduce it or control the current?

The circuit information is as follows:

I am switching S4 and S3 with a 60Hz (in sync with grid) pulse train with 0.5 duty cycle. S1 and S2 are switched at 60 kHz with sinusoidal pwm. Duty cycle = (Vc_peak/Vdc)* sin(2*pi*60*t). S5 and S6 are inactive. enter image description here

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When I measure the grid (final output, right side) voltage and current , I get this. Notice that the current wave is not biased at zero! enter image description here .

This graph includes the measurements at the primary side of the transformer, i.e. inverter output. Vc is the inverter output voltage, showing average for clarity. Vs is the sine output voltage after the inductor. Is is the current through the inductor. Igrid is inverted in this graph to match the signs. enter image description here

.

Switching waveforms:

Duty cycle of S1. The graph shown is a graph (sine at 60Hz) of duty cycle, actual switching is at rate 60kHz : enter image description here Duty cycle of S2 = (1 -Duty cycle of S1). S2 = not S1.

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Signal waveform for S4: enter image description here

T = 1/60. 50% duty cycle. S3 = not S4.

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  • \$\begingroup\$ Show gate waveforms. \$\endgroup\$ – winny Oct 25 '17 at 15:10
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    \$\begingroup\$ S5 and S6 have their inputs floating, not off. \$\endgroup\$ – τεκ Oct 25 '17 at 15:11
  • \$\begingroup\$ @winny, I'll get back to on that later today. @ τεκ , should I force them to zero then? \$\endgroup\$ – Remian8985 Oct 25 '17 at 15:14
  • \$\begingroup\$ @winny, Added. Please see above. \$\endgroup\$ – Remian8985 Oct 25 '17 at 16:12
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    \$\begingroup\$ Just curious, why are S5 and S6 in there at all? Are they relics from another circuit? \$\endgroup\$ – calcium3000 Oct 25 '17 at 17:36
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Basically, a voltage inverter is a voltage source. And the grid is also a voltage source.

So, in a grid-tied voltage inverter, you connect two voltage sources with only a (small) inductor in between.

The current in the inductor is given by:

$$ i(t) = \frac{1}{L} \int {(v_I(t) - v_G(t)) dt } $$

where \$ v_I(t) \$ and \$v_G(t)\$ are the inverter and grid voltages respectively.

The DC offset you observe certainly depends on the value of the integral from the beginning of the simulation to the time you begin to plot your current. If you change (slightly) the time offset between inverter command and grid voltage, the offset will change.

Real grid-tied inverters, cannot operate without a current loop which measures the current in the inductor and drives the inverter in order to obtain a given (usually sinusoïdal) current reference.

If you do not put this control loop, any small difference between the inverter command (and thus voltage \$v_I(t)\$) and the grid will make the current diverge.

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it looks like your Vgrid may be a DC supply, also your inverter does not appear to be synchronised to the Vgrid,

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