I would like to have some variable length generic in my entity however it looks like the default range direction is
to what collides with internal signals ranges that are declared with
entity my_entity is generic ( GEN: std_ulogic_vector := b"100_0000_0000_0000_0000_1000" & b"0000_0000_0000_0000_0000_0000" & b"0000_0000_0001" ); port ( clk: in std_ulogic; reset: in std_ulogic; a: in std_ulogic_vector(63 downto 0); b: out std_ulogic_vector(63 downto 0) ); end;
Is there any language specific mechanism to inform VHDL tools that range direction of GEN is
to? Right now, the only solution I can think of is to use some extra constant in declarative part of architecture with the same value but different range direction.