(System)Verilog: signal is x or 1 depending on placement of concurrent blocks in the code?

Question

I'm basically aware that the Verilog scheduler is inherently indeterminate, but I really don't understand why that's the case with the following code (I've simulated both cases with Icarus and Incisive on EDA Playground). The differences between the TB_A and TB_B is in the order of the initial and always blocks.

Case A:

module TB_A ();

reg nrst;
reg signal;

initial
    nrst = 1'b0; 

always @(negedge nrst)
    signal = 1'b1;

initial
    #10 $display("value is: %b",signal);

endmodule

Case B:

module TB_B ();

reg nrst;
reg signal;


always @(negedge nrst)
    signal = 1'b1;

initial
    nrst = 1'b0; 

initial
    #10 $display("value is: %b",signal);

endmodule

I would expect that at T=0 the transition on nrst occurs and inevitably triggers the always block, putting signal at 1. This happens in Case B but not in Case A, where is displayed the value x for signal. In other words I wouldn't expect indeterminacy in this case, but evidently I'm missing something. Switching to SystemVerilog doesn't change anything.

Answer 1

People misunderstand the simulation behavior of always blocks. It does not execute at every negedge. It is a process just like an initial block that executes procedural statements. It the same as if you wrote

initial begin
    nrst = 1'b0; 
    end
initial begin
  @(negedge nrst) // this means suspend the process and wait for a negedge
    signal = 1'b1;
 @(negedge nrst)
    signal = 1'b1;
  ... // repeats infinitely for an always block
   end

This is a race condition because the order that initial blocks start their processes determine if the assignment to nrst in one process is seen by the other process that suspends waiting for a negedge transition. A NBA assignment to nrst as well as moving the assignment after time 0 would solve this race.