Can someone please explain to me why the output of this level-shifting circuit starts charging from around 2.8V to 5V, and NOT from 3.3V to 5V.

At the time where the output is at 5V there is a 3.3V potential at the source and gate terminal.

So i thought that the drain-source capacitance and the gate-drain capacitance would ramp up from 3.3V to 5V.

below is the circuit diagram and oscilloscope pictures. I get the exact same results when simulating the circuit, so i am definitely missing something. enter image description here

enter image description here


After studying my simulation a bit more:

enter image description here

This is what it looks like when i zoom. The voltage is initially 3.3V. Could this be due to reverse recovery??? so that the body diode conducts in the reverse condition for a short period of time. Could that be why the source voltage goes to 2.7V because of a diode drop?


2 Answers 2


Consider this simplified capacitor MOSFET model... In this model, all switches switch at the same time, so when the input switches the short across C3 is removed.


simulate this circuit – Schematic created using CircuitLab

When it initially switches the gate jumps up to 6.6V and the drain to 3.3V. The gate charge quickly drops down to zero and C2 discharges into C3 (Cds) creating a negative Vds voltage. With equal capacitances, and the diode disconnected, the output would reach half 3.3V. Thereafter the capacitors are charged though R1.

enter image description here

With the diode connected across C3, it prevents the output dropping under Vf below the input voltage. Which is what you are witnessing.

enter image description here

Of course the real model is more complicated than that and includes inductances, but for the scope of your question at hand, this model is sufficient.

As for the capacitance. If you look at your scope trace you will see that the charge is almost linear as it first rises. This is because the capacitance falls as Vds increases.


It depends on FET diode and Vgs.

  • dV/dt = Ic/Coss

  • Icoss= (5V-Vds)/ R when Vgs

  • initially when FET is turned off, the body diode causes Vds =Vgs-Vf

When Vgs goes to 3.3 and Vds goes to 3V the rest is probe capacitance ?? pF +Coss and R pullup

Here your rise time is 2 us thus C=t/R=2us/10k=200pF This is consistent with fig 5 on your missing data sheet. For Coss vs. Vds

This explains your results.

Remember this.

  • low RdsOn FETs will have high Coss and Coss(Vds)*RdsOn(Vgs) = FoM a figure of merit that changes with FET design and Vgs max
  • \$\begingroup\$ De nada, from Sevilla Spain \$\endgroup\$ Oct 27, 2017 at 9:33
  • \$\begingroup\$ Tony can you explain why 200pF seems to give me the correct rise time, when it should be closer to 600pF according to the datasheet? \$\endgroup\$
    – MatBE
    Oct 27, 2017 at 10:49
  • \$\begingroup\$ But why is that? when Vgate and Vsource is at 3.3V, Vdrain is at 5V. Why are there a voltage drop of 0.6-0.7 between the gate and source when Vgs = 0V ??? \$\endgroup\$
    – MatBE
    Oct 27, 2017 at 12:14
  • \$\begingroup\$ @MatBE never mind... I got that wrong.. \$\endgroup\$
    – Trevor_G
    Oct 27, 2017 at 12:26
  • \$\begingroup\$ I have just updated my post with a new simulation screenshot. Would you take a look at it and tell me if my theory could be right? \$\endgroup\$
    – MatBE
    Oct 27, 2017 at 12:29

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.