I am trying to understand how much time required in fpga time slots to fetch 128 bite value from DRAM3. I have a fpga board with 100 Mhz chip that talks with DRAM3 1600 Mhz. Thanks

  • \$\begingroup\$ Find the max data rate of the comm channel and then add overhead. Divide 128 bites by the max data rate + overhead. \$\endgroup\$ – Voltage Spike Oct 29 '17 at 5:37

In general, DRAM access time depends on many factors:

  • actual DRAM timings and frequency
  • bus width
  • whether operations access open or precharged rows and whether they are "pipelined"
  • page and power policies of the DRAM controller
  • internal details of the DRAM controller

If an order of magnitude estimation is okay, worst-case random access latency should be somewhere between 50 and 100 ns assuming no power saving modes are used.

ADDED: this also assumes the DRAM controller in the FPGA does not introduce its own latencies.


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