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While researching the standard method of measuring fall time (and rise time) it seems to be standard to take the start and end points for measurement to be when the curve is at 90% of the maximum and 10%. However, I'm having trouble pinpointing an exact reason as to why this is. Any help would be appreciated!

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    \$\begingroup\$ Because it may not reach 0%/100% for many, many times the "rise"/"fall" time, if ever. \$\endgroup\$ – Ignacio Vazquez-Abrams Oct 29 '17 at 15:58
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    \$\begingroup\$ As @IgnacioVazquez-Abrams mentions the last part usually takes exponentially longer. With logic signals you don't really care since once you pass the logic threshold, how long it takes to finally settle out is not so important. \$\endgroup\$ – Trevor_G Oct 29 '17 at 16:05
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    \$\begingroup\$ As a note, some high speed serial links (Infiniband, PCI express for example) measure rise and fall times between 20% and 80% of the transition. \$\endgroup\$ – Peter Smith Oct 29 '17 at 16:09
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10% to 90% has evolved as a de facto standard. It could easily have been 20%-80%, or 5%-95%. But it wasn't.

When you make a measurement, you want it to be reproducible, which means going through the trigger point with a reasonable slope.

When you make a common measurement, you want it to cover as many cases as possible.

Using nice round numbers like 10% and 90% has satisfied enough people on these two points that they keep using it, even though it might not be exactly right for the specific system they're using.

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The reason is that the rise/fall voltage curves are actually exponential RC charging curves. The output resistance of the chip charges the capacitance of the wires and inputs connected to it, forming an RC lowpass. The output voltage of the chip might in fact never reach 100% of the supply voltage, especially if there's a DC load on the output which causes additional voltage drop across the output's internal resistance.

10%/90% is chosen because pretty much any logic input will recognize these levels correctly as low/high. TTL, for example, runs at 5V and recognizes anything below 0.8V as "low". 10% of 5V is 0.5V, so after the specified fall time of the logic output, any connected TTL input is guaranteed to recognize the voltage level as "low". It doesn't matter how long it takes to reach the full output voltage level as long as the logic threshold is passed quickly.

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    \$\begingroup\$ While your answer is generally correct, the initial "exponential RC charging curves" assertion is only occasionally true. It certainly isn't true for op amps being driven to limit, it isn't true for logic signals. In general, it's only true for fairly pure first-order systems, and that criterion is pretty rare in the real world. You might try fitting a logic signal to an RC curve with any substantial length of wire connecting transmitter and receiver. \$\endgroup\$ – WhatRoughBeast Oct 29 '17 at 17:25
  • \$\begingroup\$ @WhatRoughBeast Logic outputs, especially CMOS ones, do behave quite resistive when their voltage is almost at the supply rails. The datasheet of most Atmel microcontrollers has nice graphs of output voltage vs. output current where the resistive behavior is obvious. And CMOS inputs are purely capacitive as well, resulting in a nice RC lowpass. \$\endgroup\$ – Jonathan S. Oct 29 '17 at 18:03
  • \$\begingroup\$ When looking at the edges of logic signals, you are likely to run into transmission line effects. For example, see the output waveforms in this application report. \$\endgroup\$ – CL. Oct 29 '17 at 22:34
  • \$\begingroup\$ @JonathanS. - Please read ALL of my comment. You clearly haven't done much logic analysis with 6 inches of wire involved. Ringing and overshoot are not remotely similar to single-pose RC circuits. And "voltage is almost at the supply rails" really doesn't help. If you take a sufficiently restricted regime, you can find almost any behavior you desire. \$\endgroup\$ – WhatRoughBeast Oct 29 '17 at 23:16

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