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Some development boards have multiple DDR4 chips. Does it imply that such boards have multiple DDR controllers and memory can be accessed in parallel.

For example this boards: https://www.xilinx.com/products/boards-and-kits/kcu105.html#hardware has 4 DDR4 chips.

Thanks

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Unlikely.

The spec for that shows 64bit wide chunk DDR4. Each of those four chips will be 16bit wide, and all four wired in parallel gives 64bit.

In all likelihood (you can check with schematics), each of the four DDR4 chips will share the same physical address lines, thus preventing using them individually.


From the specifications on the page you link to:

Memory

2GB DDR4 component memory (four [256 Mb x 16] devices) at 1200MHz / 2400Mbpsps

Note the "four [256 Mb x 16]" - four 16bit devices. Then from the diagram it shows 64bit DDR4. Thus they must be wired in parallel to get the full data width.

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Yes and no. The four chips (256Mb 16 bit) are wired in a way so that they look like one single 64 bit wide memory chip and the board uses a single memory controller for all four chips. You can only access one address at a time, but you can transfer up to 64 bits of data per access.

You can find this info in the board's user guide, chapter "DDR4 Component Memory". In the pin list for the memory chips, you'll find 64 data pins and only one set of address pins that's wired to all four memory chips.

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Generally speaking, the number of chips does not imply the number of controllers.

As you say, the chips on board are 256Mx16, meaning they have a 24 bits address bus, 16 bits data in, 16 bits data out. Plus of course all the signals necessary for a DRAM chip to work.

Now, if you want to use them in parallel, i.e. as a single, 256x(16x4) bank, you will need the data lines to arrive separately to the FPGA, and then on the FPGA you instantiate an appropriate controller.

If in parallel means that you want to be able to access the four banks independently, then also the address bus must be separated. This adds up to 24x4 (address) + 16x4 (data in) + 16x4 (data out) = 224 pins. It seems quite a lot, I suspect that the board designers did not allow for such a huge usage of the FPGA pins.

The answer to the question is then: if the signals are routed accordingly, you can instantiate up to four controllers, if you want and have room for it, and use the chips as you wish.

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  • \$\begingroup\$ Do you know any dev board that has room for four memory controllers? \$\endgroup\$ – Tiger0 Nov 12 '17 at 6:42

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