Generally speaking, the number of chips does not imply the number of controllers.
As you say, the chips on board are 256Mx16, meaning they have a 24 bits address bus, 16 bits data in, 16 bits data out. Plus of course all the signals necessary for a DRAM chip to work.
Now, if you want to use them in parallel, i.e. as a single, 256x(16x4) bank, you will need the data lines to arrive separately to the FPGA, and then on the FPGA you instantiate an appropriate controller.
If in parallel means that you want to be able to access the four banks independently, then also the address bus must be separated. This adds up to 24x4 (address) + 16x4 (data in) + 16x4 (data out) = 224 pins. It seems quite a lot, I suspect that the board designers did not allow for such a huge usage of the FPGA pins.
The answer to the question is then: if the signals are routed accordingly, you can instantiate up to four controllers, if you want and have room for it, and use the chips as you wish.