# Choosing resistors for RTL gates

I'm interested in building a really, really simple computer I've been designing using resistor transistor logic gates like these:

(when I can get away with it)

(when all else fails!)

I'll be using 2n3904 transistors since I have quite a few on hand. I'm having trouble deciding on the resistors I'll be using though. I want to use a 5V power supply and I've decided I would like to limit the current draw of my gates to about 1mA. So, I've chosen 5.1k ohm resistors for my collector resistors. But, I'm not quite sure what value I should use for my base resistors. My primary problem is that I really don't know how to estimate the fan-out I'll get with whatever choice of resistors I make.

So what value would be best for my base resistors, and how do I at least estimate the fan-out of these types of gates?

• – jonk Oct 30 '17 at 4:36
• Let me know if that doesn't answer all your questions. – jonk Oct 30 '17 at 5:42

I also have a lot of certain transistor types. For example, over 26000 of the PN2222A variety. (Which are packaged quite tightly, luckily.) I have so many because I give them away to students and got them very, very cheaply.

I don't know what you intend, as you don't really say much. But my earlier discussion here covers almost all the important points you'd need to manage to make this work well. (It also implements a full adder using 9 transistors in RTL -- not to be confused with another RTL, register-transfer level, which is more applicable to ASIC design.)

All gate designs require specifications. You've only asked about fanout. But you didn't provide any specifications. Without those, there is no way to provide a serious answer to your question.

So let me make up some specifications. With the only input being your choice of $V_{CC}=6\:\textrm{V}$, I'd make these selections:

\begin{align*} 5.7\:\textrm{V} \le & \:V_{CC} \le 6.3\:\textrm{V}\\ &\: V_{HI_{MAX}}=V_{CC}\\ 60\% \cdot V_{CC} \le & \: V_{HI_{MIN}}\\ & \: V_{LO_{MAX}} \le 20\% \cdot V_{CC} \\ 0\:\textrm{V}=& \: V_{LO_{MIN}} \end{align*}

In terms of fanout, the gate must be able to accept all of the inputs simultaneously at $V_{LO_{MAX}}$ and, while fully loaded at the output with $N_{MAX}$ inputs tied to it, still maintain an output voltage greater than $V_{HI_{MIN}}$. (This means that with all of the inputs sourcing the maximum allowed current for a "0" to the base node, that the transistor still remains sufficiently off so that the output isn't dragged below $V_{HI_{MIN}}$.)

The other corner case isn't about fanout but instead requires the gate to accept all of its inputs but one tied to $V_{LO_{MIN}}$ and have the remaining one tied to $V_{HI_{MIN}}$ and, without any output loading at all to help, maintain an output voltage less than $V_{LO_{MAX}}$. (This means that with all but one input sourcing no current at all to the base node and only one input supplying the minimum allowed current for a "1" to the base node, that the transistor remains sufficiently on so that the output is held below $V_{LO_{MAX}}$ without any help from added loading on the output.)

The following arrangement isn't quite good enough:

simulate this circuit – Schematic created using CircuitLab

Instead, you will definitely want to consider something like this:

simulate this circuit

Here, $V_{EE}$ would perhaps preferably be below ground. But as an acceptable compromise as part of the designing process, it can just be ground. You just need to be careful about your margins.

You will also need to account for the range of BJT parameters you are likely to experience with a batch of discrete parts. In general, this means about a factor 2 variation in $\beta$ (for example, from 150 to 300) and a factor of 3 or 4 variation in $I_{SAT}$.

For the most part, the $\beta$ variation merely means that you use the minimum value you expect; and a separate value for "saturation mode" (such as 10 or 15.)

The value of $I_{SAT}$ means a variation in $V_{BE}$, which is important in determining where you set your base node voltage thresholds. For example, even if you assume a variation by a factor of 3 in either direction, then you will expect a variation of $V_{BE}$ of about $26\:\textrm{mV} \cdot \operatorname{ln}\left(3\right)\approx 29\:\textrm{mV}$ around the midpoint. Considering the base node voltage of $400\:\textrm{mV}$ as off and a base node voltage of $600\:\textrm{mV}$ as on would probably mean that you'd be okay as $430\:\textrm{mV}$ is probably sufficiently far from $570\:\textrm{mV}$ that part variation won't kill your design. (Remember that the collector current varies by a factor of 10 for each $60\:\textrm{mV}$ and so a factor of more than 200 in terms of collector current.)

With these thoughts and the other page I already linked for you, I suspect you should be able to work out the fanout for any particular design you make. I've provided the important boundary conditions to check, both in terms of input and output arrangements to verify the gate as well as variations in BJT parameters to consider. (Resistor values of 1% are easy to get and so you can probably just take those values as given -- though if you find yourself near any margins you probably should include this variation as well.)