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I was considering the synchronous design model.

If I understand it correctly, it can be represented as so : enter image description here

(excuse the awful schematic made with Paint)

The state switches within a stage are conditionned by the states of the previous stage and are triggered on the rising edge of the clock.

What I wondered was the following: on the rising edge, the stage number n switches, but so does the stage n+1, whose inputs are function of the states of the stage n.

That would mean the switch of the D input of a flip-flop is simultaneous to the clock, which lead to an indeterminate state of the flip-flop.

The problem may be solved if there is some delay between the Q outputs of the stage n an the D inputs of the stage n+1, and that delay should be greater or equal to the hold-time of the flip-flops of the stage n+1.

But that would mean that the circuit wouldn't work for any flip-flop.

Am I wrong ?

Thank you

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  • \$\begingroup\$ "But that would mean that the circuit wouldn't work for any flip-flop." I'm not following your reasoning here, why do you think this would be a problem? \$\endgroup\$ – Finbarr Oct 30 '17 at 15:44
  • \$\begingroup\$ The D input of any flip-flop of the circuit holds until the state of the previous stage changes. And the previous stage state change is triggered by the clock, that means it changes on the clock. \$\endgroup\$ – Jean-Paul Oct 30 '17 at 15:46
  • \$\begingroup\$ So, the D input switches on the clock, what is pretty bad, because the D input must hold a certain time (the hold-time) \$\endgroup\$ – Jean-Paul Oct 30 '17 at 15:47
  • \$\begingroup\$ And if you change one particular flip-flop, it may have a different hold-time. \$\endgroup\$ – Jean-Paul Oct 30 '17 at 15:48
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    \$\begingroup\$ Ok! That mean it's not a consequence of the synchronous design. It's just that hold-time is in practice so negligible compared to the propogation delay of all that stuff that it's never a problem. \$\endgroup\$ – Jean-Paul Oct 30 '17 at 16:02

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