I was considering the synchronous design model.
(excuse the awful schematic made with Paint)
The state switches within a stage are conditionned by the states of the previous stage and are triggered on the rising edge of the clock.
What I wondered was the following: on the rising edge, the stage number n switches, but so does the stage n+1, whose inputs are function of the states of the stage n.
That would mean the switch of the D input of a flip-flop is simultaneous to the clock, which lead to an indeterminate state of the flip-flop.
The problem may be solved if there is some delay between the Q outputs of the stage n an the D inputs of the stage n+1, and that delay should be greater or equal to the hold-time of the flip-flops of the stage n+1.
But that would mean that the circuit wouldn't work for any flip-flop.
Am I wrong ?