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I am designing a 8b10b encoder in SystemVerilog. The circuit has the ability to encode 1-16 bytes (8 bits/byte) in a single clock cycle.

I have a question regarding calculating the running disparity (RD), which is a single bit output. I understand it represents the difference between no. of ones - no. of zeros in a bit stream. Neutral disparity implies difference is 0.

The calculation is straightforward when the input is a single byte. But if I have 3 bytes to encode at once, how do I go about calculating RD?

  1. First, I encode each byte separate to form a 30b output.

  2. Do I take the 30b (3x10) encoded output and calculate RD, i.e., RD(out[29:0])?

Or

  1. Do I calculate RD(out[9:0]), RD(out[19:10]), and RD(out[29:20]) separately and then decide whether to maintain or invert current RD?

Thanks.

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1 Answer 1

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I found an answer in this paper on page 10/11.

http://domino.watson.ibm.com/library/CyberDig.nsf/papers/F2DF32762A248AE685256F48006B24E6/$File/rc23408.pdf

Running disparity is calculated at byte level and chained together. With some more sophisticated logic, the 'chaining' behavior can be short circuited.

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