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I'm looking at including a buck converter to power a 3.3V microcontroller, and I used TI's Power Designer to generate a recommended layout for my parameters.

I noticed that the copper planes are quite large here compared to the footprints of the components involved. I understand the value in having a plane for the ground, since it's a common reference point, but why are there such large areas for the other connections? Is it for heat dissipation, or other reason(s)? (Or am I misunderstanding something about how to read the diagram?)

PCB layout generated by Webench

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    \$\begingroup\$ The large copper planes minimize inductance, increase current handling and also work as a heatsink. What is true for ground planes is also true for the in and outputs. I mean, ground is just a reference point. The signals in switched converters often have large current spikes and sharp edges. Then minimizing inductance and increasing current handling capability is essential. \$\endgroup\$ – Bimpelrekkie Nov 2 '17 at 7:03
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Lower track impedance

In a switching regulator, the track impedance matters a lot. Not only resistance, but also inductance, and both are reduced when using wider tracks (or planes).

Heatsinking

A switching regulator produces heat, which has to be channeled out of the component. Copper is a very good heat conductor and is used as radiator in many switched mode power supply designs.

PCB Manufacturing issues

When producing PCBs, manufacturers often ask for a certain percentage of each layer to be copper. This is to ensure an even thickness on the whole PCB in the plating phase, as well as an uniform expanding and shrinking under temperature variations.

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Heat and low impedance for the high current paths. Some of the land area on this board might be non-critical but when you have the empty board space it provides a little extra safety margin.

It is generally not a good idea to create a large land area for the switching node (probably on the lower right of this image, but hard to tell without part numbers/schematic/etc) because the fast edges on the switching node can be an EMI problem and the large land area creates both an antenna and capacitively (sp?) couples the signal to the ground plane and possibly other traces which can create ground noise.

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  • \$\begingroup\$ It is the switching node, at least if I understand the schematic correctly. Is the size in the current layout "large"--should it be smaller? \$\endgroup\$ – chrylis -on strike- Nov 2 '17 at 15:47
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    \$\begingroup\$ That depends on a comprehensive thermal analysis, the frequency of operation of the SMPS, the rise and fall rate on the switch, the DCR of the inductor and at high frequency the core losses among other things. SMPS design is not black magic, but it is involved and requires a good background in formal theory. That is why TI and others provide online SMPS design tools that do most/all of the analysis for you. \$\endgroup\$ – Dean Franks Nov 3 '17 at 2:38
  • \$\begingroup\$ Thanks, I'll try to go with the off-the-shelf layout, then. I have just enough formal E&M to look at this, say "hey, there's complex analog going on!" and ask someone else. \$\endgroup\$ – chrylis -on strike- Nov 3 '17 at 5:41

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