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So I designed this Half-Bridge Mosfet Driver for 48V. Since I'm pretty new to this type of circuit I would like to ask if there are going to be any problems with this circuit. (eg. speed, power loss, voltage limit) The target frequency is going to be at about 60KHz, PWM modulated and 2 of those circuits are going to be configured as a H-Bridge, driving a resistive load.

The 2 Transistors marked with ULN are going to be 2 ULN2803A stages. CLK is the signal input.

If you see any problems, please let me know. Thanks.

Mosfet Driver

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  • \$\begingroup\$ What MOSFETs are you using? \$\endgroup\$ – Oskar Skog Nov 2 '17 at 16:48
  • \$\begingroup\$ N-Channel: STP55NF06LFP P-Channel: IRF5305PBF \$\endgroup\$ – fishkiller2 Nov 2 '17 at 16:50
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You don't have any dead-band, so one FET will be turning off while the other is turning on. The result will be a large 'shoot-through' current during the transitions when both FETs are partially on.

I simulated your circuit in LTspice, using FETs with similar Gate charge specs to yours. The result:-

enter image description here

Gate voltage (Blue, Green) changes relatively slowly due to the limited drive current available, particularly during the flat spot when Drain voltage is changing and Miller effect increases the apparent Gate capacitance. During this time both FETs are partially on and Drain current (red) spikes up to 180-200A. This high current will quickly heat up the FETs and burn them out, perhaps violently if one of them becomes a dead short.

Shoot-through can be eliminated by adding a delay to the Gate turn-on so that one FET is fully off before the starts to turn on. This can be done using a series resistor and paralleled diode in the Gate drive circuit. The resistor combined with Gate capacitance increases charging time, while the diode allows it to discharge at (almost) normal speed.

schematic

simulate this circuit – Schematic created using CircuitLab

Unfortunately this simple solution won't work properly in your design because the 35V Zener forces both Gate drives to have the same waveform, working against the Gate delay circuits. You could add delays at the digital inputs using a similar circuit, or provide separate clocks which have dead-band built-in (an option on many MCUs with PWM motor control).

However even if you solve the dead-time issue, at 60kHz the Gate charge and discharge times are a significant proportion of the PWM cycle time, which increases FET switching loss even without shoot-through. You need a driver which can supply more current to charge the FET Gates quicker and has a deadtime to match.

Rather than trying to develop a discrete circuit I would use a half-bridge driver IC such as the IR2103. It is designed to use all N-channel FETs, which may be easier to obtain and more cost effective. These drivers require a supply voltage of 12-15V, but at relatively low current which could be derived from the main supply via a linear regulator.

One possible issue with the IR2103 is that the high-side drive is 'bootstrapped', so it requires continuous PWM pulses and won't work with a full-on signal. Provided your clock always has a reasonable PWM ratio this should not be a problem. If you require 0-100% PWM then choose a driver which has an on-board charge pump.

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  • \$\begingroup\$ Thanks for the long answer. What about using an IR2111 as a driver? \$\endgroup\$ – fishkiller2 Nov 3 '17 at 9:43
  • \$\begingroup\$ Yes, IR2111 is another option. \$\endgroup\$ – Bruce Abbott Nov 3 '17 at 14:13
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An extremely poor circuit overall. To model it you really need to include 1600 pf across each of the driver transistors C-E. Points to consider:

  1. You have very little headroom in your VDD P-Channel FET selection. I'd suggest you need at least a 60 V or above FET.
  2. Turn on times are slow because each driver depends on the C(in) discharging on the opposing FET.
  3. You are very close to exceeding the reverse V(BE) ratings of your driver transistors.
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