The output change when i connect it with the other circuit

Question

Two symbols are the same sample and hold,so Theoretically their ouput should be the same,but as we see,when i connect it with a comparator,the output of sample and hold totally change.

Why?How do i improve this?add a unit gain amp at the output of sample and hold?By the way,the red one seems read the comparator clock.

duty cycle of clock for sample and hold:85%

duty cycle of clock for comparator:50%

Answer 1

The blue curve is an ideal scenario where there is no load where as the red waveform is more realistic as the gate capacitor of amplifier acts as load. Blue curve however is not achievable but it can be much better than red one.

The tweeks to improve output after sample and hold can be done:

• Changing hold capacitor
• Reducing Ron of Sample switch
• Reduce input capacitance of amplifier
• Use a dummy transistor after the sample switch to reduce the non-linearities

All this are provided in "Design of Analog CMOS circuits" by B.Razavi though only analysis.

Answer 2

I have improve that by adding two buffer,which is two stage amp