1) For table 1 of Berkeley paper , why "Input must be valid for at least two clock periods in the new domain." ?
the width of the input pulse must be greater than the period of the synchronizer clock plus the required hold time of the first synchronizer flip-flop. The safest pulse width is twice the synchronizer clock period.
Could anyone tell why it has to do with hold time of the first synchronizer flip-flop ?
2) For pulse synchronizer or what we known as toggle synchronizer, I do not understand the explanation highlighted in yellow that is given below:
One restriction of a pulse synchronizer is that input pulses must have a minimum spacing between pulses equal to two synchronizer clock periods.
This problem is more severe when the clock period of input pulse is greater than twice the synchronizer clock period