I've procured FPGA cores from two different vendors, both written in VHDL. Both cores have a type defined called ahb_slv_out_vector but the two types are not compatible. I need to use both types in my top-level module but there is an obvious conflict.
The libraries are imported from
work.amba.all
and
<vendorname>.amba.all
How can I disambiguate the two type names in my top level module while allowing other files that import them to continue using them with their current name?