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I've procured FPGA cores from two different vendors, both written in VHDL. Both cores have a type defined called ahb_slv_out_vector but the two types are not compatible. I need to use both types in my top-level module but there is an obvious conflict.

The libraries are imported from

work.amba.all

and

<vendorname>.amba.all

How can I disambiguate the two type names in my top level module while allowing other files that import them to continue using them with their current name?

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1 Answer 1

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The libraries are imported from
work.amba.all
and
vendorname.amba.all

No they aren't.

They are imported from work.amba and vendorname.amba. The all in the use clauses simply pollutes your namespace with everything in both of those libraries.

So, don't do that.

Instead, use fully qualified names

Use work.amba;  
Use vendorname.amba;  
... 
signal Mine   : work.amba.ahb_slv_out_vector;
signal Theirs : vendorname.amba.ahb_slv_out_vector;

and the two signals will coexist quite happily. Note they are completely different types, so you'll probably have to write type conversion functions between them if they should ever meet.

If most of your code involves the Work library with a few rare exceptions from the other, then you can happily use work.amba.all; to reduce the number of fully qualified names, only using them for the other library.

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  • \$\begingroup\$ Perfect, I think that should do it. I will know for sure when I get back to work on Monday. \$\endgroup\$
    – kjgregory
    Nov 3, 2017 at 21:26
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    \$\begingroup\$ You can also declare subtypes subtype SV is vendorname.amba.ahb_slv_out_vector; to make life easier (and code prettier) \$\endgroup\$ Nov 3, 2017 at 21:30
  • \$\begingroup\$ I would recommend an alias instead of a subtype. \$\endgroup\$
    – Paebbels
    Nov 3, 2017 at 22:03
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    \$\begingroup\$ The declaration of the same name in the second use clause is not made directly visible (IEEE Std 1076-200, 12.4). That leaves visibility by selection with Brian's selected names (8.3). As Paebbels doesn't explain aliasing a type can potentially have fewer side effects than subtypes, both require making declarations in an inner declarative region hiding otherwise directly visible declarations (12.3). When an inner declarative region can't be used you can just use selected names. A type name in the type mark of a subtype indication can be a selected name (6.3, 8.1). \$\endgroup\$
    – user8352
    Nov 3, 2017 at 22:21

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