Only a partial answer because I don't have all of them.
First a comment on this statement: "I figure that this would be done in the space of two cycles".
Actually, every single bus access consists of 8 "states", each state being either the positive or negative part of the main clock. Thus, a single bus cycle is always 4 clock cycles. (This annoys me more than it should, but that's another story.) You probably know this if you're asking these questions but it doesn't hurt stating it.
Data Load Order
The data load order is actually documented in the M68000UM/AD:
Each data type is stored in memory as shown in Figure 2-6. The numbers indicate the order of accessing the data from the processor.
...or is it? Now, that figure is a little confusing to me, but as far as I can interpret it, integers are always read from memory beginning at the lower address.
I could not find any documentation about this, but I will take my chances and make a guess: I don't think so.
Take for example the arguably simplest instruction,
AND.W (A0),D0 vs.
AND.L (A0),D0. The 16-bit version takes 4 cycles for reading the single instruction word, and 4 cycles more for the
(A0) effective address, which is simply another 16-bit read, for a total of 8 cycles.
The 32-bit version specifies 6 cycles: 4 to read the instruction, 2 extra "unknown" cycles, and 4 cycles to read the 16-bit data, a total of 10 cycles.
I don't know why but to me this indicates that the ALU is processing the 16 bits of data one after the other, with some extra time necessary to shuffle everything. This invisible shuffling would not be necessary if it had a buffer. Maybe this does not make sense when I read it again.
The execution model does not seem to be documented. For word-sized operands, execution is "hidden" in the operand read cycle. The only hint I can find in the documentation is section 5.1.3 Read-Modify-Write Cycle. The state information shows:
The bus signals are unaltered during S8-S11, during which the arithmetic logic unit makes appropriate modifications to the data.
Four states equals 2 clock cycles.