I am trying to make a clock divider commanded by 2 bits :DTPS. For instance if DTPS is:
- "00" we get the clock as output(2^0)
- "01" we divide the clock by 2 (2^1)
- "10" we divide the clock by 4 (2^2)
- "11" we divide the clock by 8 (2^3)
So i had 2 problems the first is when DTPS is "10" divison becomes 11111111111111111111111111100 I don't know why. and the second problem is that I manged to get an impulse when the DTPS ="01" but i could not make a full signal which the division of clk.
Please review my code and tell me what I i did wrong and how could the right thing that I did be improved as well as my coding style.
Thank you very much.
library IEEE; use IEEE.STD_LOGIC_1164.ALL; Use ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; entity diviseur2n is Generic (Nbits : integer := 8); Port ( rst : in STD_LOGIC; clk : in STD_LOGIC; DTPS : in STD_LOGIC_VECTOR(1 downto 0); tc : out STD_LOGIC); end diviseur2n; architecture architecture_diviseur of diviseur2n is signal cpt : std_logic_vector(Nbits-1 downto 0); signal division : integer; signal cpt_full : std_logic; begin process(clk) begin if DTPS="00" then division <= 1; else division <= to_integer(signed(DTPS))*2;-- value of DTPS into decimal then *2 to get 2^n= divison end if; end process; -- compteur 0 a division comptage: process(clk,rst,division) begin --cpt_full <= '0';give this error: Signal cpt_full cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release. if rst = '1' then cpt <= (others => '0'); cpt_full <= '0'; elsif rising_edge(clk) then if cpt < division then cpt <= cpt + 1; else cpt <= (others => '0'); cpt_full <= '1'; end if; end if; end process comptage; -- impulsion de sortie a division retenue: process(cpt_full) begin if cpt_full='1' then tc <= '1'; else tc <= '0'; end if; end process retenue; end architecture_diviseur;