enter image description here

I want to determine the input pattern for the worst case tpHL of this CMOS gate. I think there may be more than one input pattern that give worst case tpHL. The following is my reasoning: The petterns: 0010>0111, 1010>0111,0000>0111 and any other pattern where the initial state has D=0 (and final state 0111 or 1011), give worst case tpHL, as in these cases the 2 internal node capacitances (in red) are charged initially and need to be discharged in addition to load capacitance (in blue). Is this reasoning correct or is there a difference in delay between all these input patterns that I'm not accounting for?

  • \$\begingroup\$ The reasoning is correct that the foot transistor "D" is to be turned on last. But only one pattern will give you the worst case delay. Try simulating with HSPICE! \$\endgroup\$ – ammar.cma Nov 4 '17 at 1:30
  • 2
    \$\begingroup\$ @ammar.cma I'm trying to understand it conceptually, is there a way to determine without simulation which case would give worst case delay? \$\endgroup\$ – user281270 Nov 4 '17 at 1:34

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Browse other questions tagged or ask your own question.