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I am reading the MCP4725 digital-analog converter datasheet and they recomend to use two bypass capacitor at supply voltage:

The power supply at the VDD pin should be clean as possible for a good DAC performance. This pin requires an appropriate bypass capacitor of about 0.1 μF (ceramic) to ground. An additional 10 μF capacitor (tantalum) in parallel is also recommended to further attenuate high frequency noise present in application boards. The supply voltage (VDD) must be maintained in the 2.7V to 5.5V range for specified operation.

What is the advantage of using a tantalum capacitor in this application? A 0805 or 1206 10μF ceramic capacitor is even smaller than usual tantalum capacitor. Can I use just two ceramic capacitor, 100nF and 10μF?

One additional question: Is it the output voltage of this DAC stable enough for a voltage reference? Or could it require some kind of filter?

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What is the advantage of using a tantalum capacitor in this application? A 0805 or 1206 10μF ceramic capacitor is even smaller than usual tantalum capacitor. Can I use just two ceramic capacitor, 100nF and 10μF?

There really isn't an advantage other than that was the easiest way to get 10uF when that datasheet was written. In 2017, I would go with ceramic there for a few reasons.

  1. Tantalum caps can catch on fire if mistreated, at least the manganese dioxide variety. (great way to make an unsuspecting ME soil themselves, FYI) The modern polymer variety don't have this problem, but cost more.
  2. Tantalum caps have higher ESR than ceramic, which makes them tend to generate noise on power rails with pulsed loads. This is fine as a bulk cap on the input of a regulator, if the regulator has decent ripple rejection.

One thing you do need to watch out for is the decrease in effective capacitance as applied voltage increases. If you have a 6.3V cap and put 5V on it, it's possible that it's losing 80% of its effective capacitance. To mitigate this, use a cap rated for at least twice the voltage you're going to put on it.

One additional question: Is it the output voltage of this DAC stable enough for a voltage reference? Or could it require some kind of filter?

Wrong question. Since this part uses VDD as the voltage reference, you really need to ask if VDD is stable enough to act as a voltage reference. There isn't enough information here to answer that question.

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  • \$\begingroup\$ Thanks for your complete answer. Well, assuming that the VDD input is stable, will the CDA output be as stable like VDD? Or it could it generate additional noise? Is it usual to use some kind of passive filter at the CDA output like this? \$\endgroup\$ – D. Arius Nov 4 '17 at 4:11
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    \$\begingroup\$ Theoretically it should be as stable as VDD. It's likely there will be noise during any I2C communication. Noise should be the least of our concern. For a reference voltage, temperature stability is a much bigger deal, and most regulators are not very temperature stable. This device is not a good choice to serve as a voltage reference. \$\endgroup\$ – Matt Young Nov 4 '17 at 4:29
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Given PSRR of this DAC is completely unspecified, assume the high-frequency PSRR is ZERO dB; that is, 10mV of VDD wiggle at 100KHZ becomes 10mV of Vout wiggle at 100KHz.

Thus you must design the VDD network for quick dampening.

If C = 10uF and L = 10nH, the ringing Tau is 1/sqrt(10uF * 10nH) = sqrt(10^13) or sqrt(10 * 10^14) 3.16 * 10Million radian/sec or 5MHz Fring.

To dampen, have a series R of size sqrt(L/C) = sqrt(10nano/10micro) = sqrt(0.001) = 0.031 ohms. ESR of capacitors, or of 60 squares of PCB foil, may suffice.

Assume each cycle of dampening, at 5MHz or 200 nanosecond/period, achieves 6dB attenuation (Q of 1); this will vary with ESR over temperature, thus output INL or DNL will vary over temperature.

For 12 bits, you need approximately 12 cycles of dampening thus 12 * 200nS = 1.2 microSeconds per output update.

This VDD network must be designed.

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