MOSFET driver without gate resistor

Question

While researching MOSFET gate drivers I came across Microchip's MIC4605-2 and it's evaluation board:

MIC4605 Evaluation Board: 85V Half-Bridge MOSFET Drivers with Adaptive Dead Time and Shoot-Through Protection

The evaluation board does not have any gate resistors for the MOSFETS:

In fact, the datasheet for the MIC4605-2 states:

"An external resistor between the LO output and the MOSFET may affect the performance of the LO pin monitoring circuit and is not recommended."

Owing to the fact that this gate driver features adaptive dead-time and thus monitors the gate of the MOSFET to determine when it has fully turned off, a gate resistor prevents proper sensing of the actual gate.

As I understand it, the gate of a MOSFET acts like a capacitor. At t(0) any capacitor will act like a short circuit. Without a gate resistor the only thing limiting the current is the gate driver's output resistance, which is supposedly low, it would not be a good driver otherwise. My thinking is this should lead to current peaks that easily exceed the driver's 1A maximum peak current and damage the chip, but the evaluation board demonstrates that this is not the case, what am I missing?

Answer 1

The chip specifies the "typical" LO output current as 1A, not an absolute maximum. This current is limited by its internal output resistance since there doesn't seem to be a limiting circuit according to the datasheet's diagram of the output stage. It won't be able to deliver 1A (or more) continuously, however - it can only do that for short pulses. So if you just short its output to ground, it will die.

MOSFETs like the ones in the MIC4605's output stage can handle large current pulses for a short time by simply absorbing the heat generated by the pulse in their thermal mass. It's not current that kills a FET, it's overheating. If the pulse is short enough, the FET will not heat up much and therefore survive just fine.

Take a look at the datasheet of the IRLML2803 MOSFET, for example. On page 4, bottom right, there's a graph showing the maximum safe operating area (SOA) of the device. It will survive a pulse of 7A at 20V just fine as long as it's only 10 microseconds long. That's 140W dissipated in a SOT-23 device. The FET can't get rid of that heat but will absorb it in its thermal mass instead, heating up a little. As long as that doesn't cause it to get hotter than its maximum junction temperature, no harm will be done.

Answer 2

The gate capacitance of a FET is NOT an ideal capacitor. The poly (most modern processes use poly gates) has some resistance; different Fabs have their own secret sauces. The Apps Engineer likely will not have access to any Fab details.

However, even if the gate structure has ZERO resistance, the other "plate" of that parallel-plate capacitor has lots of resistance, because that other plate is the bulk material between the source and drain; initially the S & D are not conducting with the yet-unformed-channel and the resistance of that other plate includes all the bulk material and all the bulk-tie resistances (aka well-tie, for some processes).