From the first picture , the output and input should be the same,and as i see in the second picture,there is a offset voltage about 17mV.I surf the internet and realize that i have to add a high pass filter,as shown the third picture,but the offset voltage only become from 17mV to 10mV,i try to decrease or increase the value of R and C,but it does't change,so i wonder is my High pass filter right?
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\$\begingroup\$ Is the op-amp one that you defined yourself or one from a library? If it's from a vendor library, what is the input offset voltage spec for the design? 10-17 mV aren't unreasonable offset voltages for op-amps that aren't specifically designed to minimize offset. \$\endgroup\$– The PhotonCommented Nov 5, 2017 at 2:26
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\$\begingroup\$ @The Photon this op-amp is defined by me,do i need to provide its schematic? \$\endgroup\$– Shine SunCommented Nov 5, 2017 at 3:52
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2\$\begingroup\$ @ShineSun Are you saying this opamp's design is yours? You developed the schematic and you are fighting with an input offset error problem by trying to stick a filter around it?? (I'm probably not reading things right.) \$\endgroup\$– jonkCommented Nov 5, 2017 at 4:27
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1\$\begingroup\$ Yes, if it's your op-amp design, and you want to know why it has input offset, you should provide the schematic. \$\endgroup\$– The PhotonCommented Nov 5, 2017 at 4:35
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1\$\begingroup\$ @ShineSun Thanks. I just +1 you since your question is clearer now. I think you need some design help. You are not going to fix a MOSFET input opamp offset voltage error by wrapping a filter around it. MOSFETs are notorious for offset voltage error. \$\endgroup\$– jonkCommented Nov 5, 2017 at 23:41
1 Answer
This is voltage follower circuit and tendency to think that output should follow the input but this is for the varying input not the constant common mode DC voltage.
What I mean to say is that check if your Vinput Peak-to-peak = Voutput Peak-to- peak, if so then I must say its doing its job.
What you see as offset here may not be an offset itself. If needed exact copy of input at the output, then one must design the OTA such a way that certain input common mode voltage generates same output common mode. Have you considered this during your design process?
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\$\begingroup\$ NO,I don't,do you have any reference about this? \$\endgroup\$ Commented Nov 5, 2017 at 23:07
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\$\begingroup\$ A general methodology to design an OTA is given in the following link : aicdesign.org/SCNOTES/2010notes/Lect2UP230_(100327).pdf I hope it helps :) \$\endgroup\$– rsg1710Commented Nov 6, 2017 at 9:50