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Why is pin number 7 GND and 14 VCC in 7400 ICs ( logic gate ICs) ? Could the designer have put VCC and GND in some other pin number? Is there a constraint for that specific number? (Except a few cases, like 7490, Please consider gate ICs for example)

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    \$\begingroup\$ The 7490 for example has Vcc on pin 5 and GND on pin 10. \$\endgroup\$
    – Janka
    Commented Nov 5, 2017 at 2:01
  • \$\begingroup\$ Please ignore the exceptions. I've edited the question. \$\endgroup\$
    – user167930
    Commented Nov 5, 2017 at 2:08

3 Answers 3

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There are no significant constraints and early ICs i DIP packages did try a variety of pinouts.

After a few years the corner power pins dominated and most 7400 series ICs standardized with power on the corners.

It is fairly convenient for routing power on few layers on a PCB by using a grid arrangement but it is not ideal for power system integrity as it requires large loops for the decoupling network. An arrangement where the power pins were adjacent would be better from that point of view as the decoupling capacitor could be placed with very short leads.

These power pinouts only really apply to 7400 series digital ICs in DIP packages or SMT variants of the same device. Analog ICS, ASICs and others such as microcontrollers invariably use different power connections to improve power integrity.

As WhatRoughBeast commented ground connections in particular became more important as the device speeds increased.

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It did/does also make it really easy to place decoupler caps right above the DIP packages, tight to the Vcc pin in nice neat rows/columns of ICs.

When chips were in rows, the left side of the decoupler was nicely right next to the ground on the IC above it.

enter image description here

On a densely populated board that was important.

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As Kevin White has answered, the earliest 7400 chips showed a variety of ground/Vcc pins, with pin 7 and 14 (or 8 and 16 for 16-pin packages) quickly becoming the standard. This made pcb layout easier, as ground and power connections could be bussed along the rows and columns of a grid array of ICs.

However, Kevin is incorrect that there are no significant constraints, at least not always. In the 1990s, the technology had progressed to the point that logic families which maintained compatibility with 7400 started to get so fast that switching transients interacting with physical issues started producing ground bounce https://www.fairchildsemi.com/application-notes/AN/AN-640.pdf issues.

There were even a number of buffers constructed specifically to minimize ground bounce, such as https://assets.nexperia.com/documents/data-sheet/74ALVC_ALVCH16244.pdf These ICs featured multiple ground pins, and the pins tended to be located in the middle pins of a row, so as to minimize the length (and inductance) of the internal lead frame and chip bonding wires. This class of parts was largely superseded as design steered away from the physically large DIP package and toward much smaller SMT packages.

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