Can someone explain what this line means in the code for a D Flip Flop written in Verilog?

Question

module dflipflop (data  ,clk  , reset ,q);// Code for Asynchronous Positive Edge triggered D flip flop
input data, clk, reset ; 
output q;
reg q;
 always @ ( posedge clk or negedge reset)
  if (~reset) begin //what does this block of code mean?
    q <= 1'b0 // particularly this line
  end  else begin
    q <= data; // and this one
end//
endmodule

I am new to learning Verilog, and I have to learn the codes for the various types of flip-flops. However, I haven't been able to understand this one entirely and what it means.

For instance, as the D flip-flop is positive edge triggered, hence we write posedge clock and it has an asynchronous reset input apart from the normal D input.

But, what I do not understand is the use of the <= operator in the highlighted lines and what is being done there. Does it mean q is being assigned a value less than zero? What does data variable refer to in the other line, and what exactly does the line mean as well?

Answer 1

First of all, the <= is a type of assigning value to the variable. It doesn't mean less than; instead, the value zero is assigned to variable q when the condition is met.

Summary of Verilog syntax:

http://ee.sut.ac.ir/People/Courses/142/Summary%20of%20Verilog%20Syntax.pdf

if(~reset) - this means the condition is fulfilled when reset = 0 (~ is a bitwise negation operator, check the above link in the operator section), meaning when reset is zero, the statement q<=1'b0 is executed; otherwise, the input is passed to output which is given by q<=data. This is the functionality of a D flip-flop.

Answer 2

<=

is a non-blocking assignment operator used to execute the code or pass the values in concurrently (in parallel). This means that all the values are passed simultaneously, no matter the order in which the values are passed into the signal.

This is in contrast to

=

operator in which the values are passed sequentially.

Consider this code

module test;

int a=4 , b=0 , c=0;


initial begin
 a<=10;
 b<=a;
 c<=a;

$display("a=%0d  b=%0d  c=%0d \n",a,b,c) ; //Here a=4  b=0  c=0 
                                           // and the values are assigned 
                                           // to the variables in the next cycle. You can 
                                           //check this out by using the always statement 

end

initial begin

  a=10;
  b=a;
  c=a;
  $display("a=%0d  b=%0d  c=%0d \n",a,b,c) ; //Here a=10  b=10  c=10 

endmodule