0
\$\begingroup\$
module dflipflop (data  ,clk  , reset ,q);// Code for Asynchronous Positive Edge triggered D flip flop
input data, clk, reset ; 
output q;
reg q;
 always @ ( posedge clk or negedge reset)
  if (~reset) begin //what does this block of code mean
    q <= 1'b0 // particularly this line
  end  else begin
    q <= data; // and this one
end//
endmodule

I am new to learning Verilog and I have to learn the codes for the various types of flip-flops. However, I haven't been able to understand this one entirely and what it means. For instance, as the D flip-flop is positive edge triggered, hence we write posedge clock and it has an asynchronous reset input apart from the normal D input. But what I do not understand is the use of '<=' operator in the highlighted lines and what is being done there. Does it mean q is being assigned a value less than zero? What does data variable refer to in the other line and what exactly does the line mean as well?

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3
  • 1
    \$\begingroup\$ The <= means it is synchronous to the clock. \$\endgroup\$ Nov 6 '17 at 8:02
  • \$\begingroup\$ Okay. So it means the output 'q' of the flip-flop is formed synchronously and that if reset is zero, then output 'q' becomes zero. \$\endgroup\$ Nov 6 '17 at 8:05
  • \$\begingroup\$ No, it doesn't mean that it's "synchronous to the clock". Look up "non blocking assignment". NBAs handle potential race conditions in your code. \$\endgroup\$
    – EML
    Nov 6 '17 at 8:40
3
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First of all the '<=' is a type of assigning value to the variable. It doesnt mean less than; but instead the value zero is assigned to variable 'q' when the condition is met Summary of verilog syntax : http://ee.sut.ac.ir/People/Courses/142/Summary%20of%20Verilog%20Syntax.pdf

if(~reset) - this means the condition is fulfilled when reset = 0 (~ is a bitwise negation operator, check the above link in the operator section), meaning when reset is zero the statement q<=1'b0 is executed other wise the input is passed to output which is given by 'q<=data'. This is the functionality of D flip-flop.

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2
\$\begingroup\$
<=

is a non-blocking assignment operator used to execute the code or pass the values in concurrently / in parallel. This means that all the all the values are passed simultaneously, no matter the order in which the values are passed into the signal

This is in contrast to

=

operator in which the values are passed sequentially.

Consider this code

module test;

int a=4 , b=0 , c=0;


initial begin
 a<=10;
 b<=a;
 c<=a;

$display("a=%0d  b=%0d  c=%0d \n",a,b,c) ; //Here a=4  b=0  c=0 
                                           // and the values are assigned 
                                           // to the variables in the next cycle. You can 
                                           //check this out by using the always statement 

end

initial begin

  a=10;
  b=a;
  c=a;
  $display("a=%0d  b=%0d  c=%0d \n",a,b,c) ; //Here a=10  b=10  c=10 

endmodule
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2
  • \$\begingroup\$ Are you sure you mean "sequentially" and not "serially"? If it isn't parallel then it's serial. \$\endgroup\$ Nov 6 '17 at 14:47
  • \$\begingroup\$ Well, Sequential execution refers to a statement being executed only after its preceding (or one or more key fields) has done so and serial execution strictly refers to execution after its perceding statement. So, if I'd have to be precise, I'd refer to it as time-sequential or or order-of-occurence sequential. \$\endgroup\$
    – Your IDE
    Nov 7 '17 at 4:58

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