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When a multi core CPU is interrupted, the PC will be changed to point to the corresponding entry in the interrupt vector at the next instruction fetch. On a CPU having more than one core (e.g. modern x86_64 or ARM). I do not understand, which core is used to serve the interrupt. Is it always one core, such as core 0, or is it configurable? Could someone give an example for a common architecture or possibly more examples for architectures where it is handled different?

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    \$\begingroup\$ Depends on your architecture and configuration. You can get all kinds of variants. \$\endgroup\$ – PlasmaHH Nov 6 '17 at 11:44
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    \$\begingroup\$ This is very processor-specific. \$\endgroup\$ – Olin Lathrop Nov 6 '17 at 11:46
  • \$\begingroup\$ Possible duplicate of stackoverflow.com/questions/10235011/… \$\endgroup\$ – pjc50 Nov 6 '17 at 12:07
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The answer is that the inbound Interrupt does not connect directly to any core in a multicore architecture (given your question asks about Intel and ARM).

For the Intel CPU architecture models (I don't work on ARM), when first powered up there is no mapping configured so all interrupts (and indeed boot code) runs on processor zero. Once virtualization is initialized then the rules change drastically.

Interrupts arrive at an I/O processing unit and are 'mapped' in hardware to the required processor. That map definition could map all interrupts to a single core (which then could move an interrupt to a virtualized ISR on another core), or map various interrupts directly to certain cores.

A good overall example is Intel VTD on i7 where interrupts are handled by the Northbridge implementation:

enter image description here

A good document to start with is this which walks through the mapping of both interrupts and DMA for the i7.

Depending on what software is running (RTOS vs Virtualization kernel) the mapping of interrupts will vary.
An excellent paper on an RTOS implementation in Linux is here.

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