# How do you determine what the circuit that determines the next state looks like?

This is a homework question. I've only started to learn about circuits and it's just that I'm completely lost on what the circuit to determine the next state would look like. I'm looking for the process of how to make the circuit that determine the next state so I can apply it to other similar problems rather than just the circuit for this problem. So first I had to simplify a truth table. I got I got this circuit from translating the truth table to a Karnaugh map

Moving on, I had to use the circuit I made to try determine the next state which in turn lights up an LED. Something like: The state transition table: which I once again converted to two separate karnaugh maps and made a circuit for them which leads me to: This was a bit iffy because I wasn't sure how I was supposed to connect the two bit register to the circuit that resulted from the karnaugh map

The FSM has one input, the input from the very first simplified Karnaugh map

• it will count the number of ones

• if it sees a 0, it will reset the count to 0

• if it seeas a 1, it will increase its count

• if it sees at least 3 1s in a row, it will turn on an LED

• The LED will stay on until it sees another 0.

For the last part of the problem, I have no idea how to create the circuit that determines the next state. I'm relying on truth table and Karnaugh maps to make my circuits quite heavily and I'm not sure what to do without it. Any help would be appreciated.

• It's hard for me to deduce what your actual question is, do you want us to verify your truth table to karnaugh-map to gate translation? It's so many question marks for one question. – Harry Svensson Nov 6 '17 at 16:25
• Sorry, main question is how do I use the given information to create a circuit that determines the next state. – Fox Nov 6 '17 at 16:27
• As you can see in your state transition, you got 8 states, $\log_2(8)=3$, this means you need 3 D-latches. Hmmm, don't you have a designated teacher for this? My teacher had an extra session because he realized no one understood this exact thing you're describing. – Harry Svensson Nov 6 '17 at 16:55
• I'm voting to close this question as off-topic because it has been abandoned by the asker for two years leaving it unclear if they are satisfied or if there is an aspect still unresolved. Obviously the course for which this assignment applied is long over. – Chris Stratton Jul 26 at 13:31

The truth table does not imply a sequential input, just a combinational input

The logic design method is simply Karnaugh Map reduction or boolean simpliciation.

You can use Q=1 or Q'=0 since there are 9 rules where Q=1 and 7 rules where Q=0.

I chose the fewer Q'. Using Q=0 s in the output gate uses Q' output = 0 implies using a NOR gate which is preferred to OR gate since it has lower latency with 1 less inverter.

Since there are 4 groups a 4 input NOR gate is one possible solution. There may be further simplication, but there is no sequential input implied.

This result could be implememnted with programmable logic or many gates in discrete form.

A 1st cut graphical simplication looks like this. 