The elephant in the room is often getting the heat out as much as breakdown voltage at this point (Time was that was not so much the case).
For a CMOS device power is usually dominated by switching losses which go linearly in frequency and as the square of the voltage (1/2 CV^2 and all that), so going from 5V to 1V for core power is a huge (~25 times) saving in dynamic heat generation and that matters as clocks speed up.
At the same time, generating low voltages at large currents has become cheap and easy, tens of amps at 1V is trivial with a modern polyphase buck converter. While the 1V for the core, 1.2V for the DDR, 1.8V for the LVDI IO, 2.5V for the Aux IO thing is a little annoying, the inductors required to generate these do not integrate into a silicon process well (On chip magnetics tend to be poor for doing power things), so the supplies need to be separate (Besides the chip vendor cannot know what else I might be running off any given rail, so how do you size it?).
What we are seeing in modern designs is a rail of typically about 12V being regulated on card to whatever that particular circuit needs, (another symptom of cheap switchmode converters), you seldom see a supply having 12/5/3.3 outputs all taken to various circuit boards any more (at tens of amps), it is all either 12V or 48V (sometimes, -48V in the telecomms world for corrosion reasons) regulated down at point of load. This has many advantages starting with simplified wiring, and the fact that the higher bus voltage suffers less for voltage drops, and extending to the fact that an on card POL regulator can trivially easily sense the actual voltage at the load device.