How does C1 hold Vr1 when V2 is off(0-3v). I'm confused since C1 is referenced to 4V from V1. Shouldn't there be a negative charge on the "R1 Side" of C1?
Let's suppose the forward voltage of the diode is 0.3V. While the capacitor is charging, the voltage at the point on the bottom of C1 (let's call this node Vc-) is held at 2.7V, and so the capacitor charges to (4-2.7) = 1.3V. When V2 shuts off, the voltage at Vc- is still 2.7V but V2 = 0, so the diode is in reverse bias and no current flows. Thus, the capacitor starts charging up to 4V and will eventually reach it (technically it's asymptotic but you get the idea) so long as V2 stays off.
This graph can better display the behavior of the circuit (simulated in LTSpice). You can see that when V2 shuts off, Vc- begins dropping because the capacitor is charging to 4V. However, if V2 were to turn back on, the node Vc- is asserted to 2.7V and the capacitor adjusts accordingly.