I have problem with the clock signal in a Verilog testbench.
I've tried almost every possible way to create the clock, but in the waveform it is U
, meaning "Unknown".
Here is my code for clock (i_SysCLK
is my input clock):
`timescale 1ps/100fs
module sim_tb_top;
parameter CLKIN_PERIOD = 5000;
reg sys_clk_i;
reg clk_ref_i;
wire i_SysCLK;
initial
sys_clk_i = 1'b0;
always
sys_clk_i = #(CLKIN_PERIOD/2.0) ~sys_clk_i;
initial
clk_ref_i = 1'b0;
always
clk_ref_i = #REFCLK_PERIOD ~clk_ref_i;
initial
i_SysCLK = 1'b0;
always
i_SysCLK = #(REFCLK_PERIOD/2.0) ~i_SysCLK;
endmodule