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I'm dealing with a question about an implementation of a full adder with component delays.

gate schematic

  • tpd(XOR) = 5 ns
  • tpd(AND) = 2 ns
  • tpd(OR) = 2 ns

I'm having problems solving for the the propagation delay for the S and Cout outputs. How do I find the propagation delay?

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    \$\begingroup\$ Think about what kinds of gates the signals will have to go through to get to the outputs \$\endgroup\$ – jramsay42 Nov 8 '17 at 21:51
  • \$\begingroup\$ So would tpd(FA.S) = 10 nS tpd(FA.Cout) = 9 nS \$\endgroup\$ – dp4325 Nov 8 '17 at 22:48
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For each gate, write the delay value into the middle of the symbol. Then follow the signal path from the inputs to the outputs in question and add up the delays as you go. The two inputs to the last Cout gate have different delay values, so use the longest one.

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  • \$\begingroup\$ So would tpd(FA.S) = 10 nS tpd(FA.Cout) = 9 nS \$\endgroup\$ – dp4325 Nov 8 '17 at 22:14

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