Z80 I/O explanation?

Question

I have been following the two Great Z80 Project guides and the only thing I don't get is the I/O. He uses a 6522 I/O V.I.A. and I don't quite understand the idea of I/O ports. So my question is, how do I hook more than one 6522 to the CPU so I can control more peripherals?

Answer 1

Wow this question certainly brings back memories. If I recall correctly, you can just use a 74HC573 octal latch IC to get you some outputs, and a 74HC244 octal buffer for input ports. You connect the latch ports to the Z80 data bus and then need to add an address demultiplexer to some of the A lines (such as a 74HC138) which allows you to choose which latch/buffer gets activated when you read or write to an address. Beyond these parts it was just a case of hooking up the correct output enable/latch pins to the Z80.

I never used the 6522 but it appears to be a sort of 'all in one' peripheral solution that includes IO ports and timers. Some consider this cheating compared to a full logic gate solution if you are after the 'full' Z80 experience.

Answer 2

For the 6522 to work, both CS (Chip Select) pins must be active. The trick here is that CS1 is active-high and CS2 is active-low; So tie CS1 to the high side of your power supply and CS2 to the low side.

Great Z80 project goes on with I/O accesses, finding a way to bring 6522 to life every time the Z80 does an *I/O cycle. 6522's CLK2 pin is driven:

We can easily substitute the Z80's "I/O Request" (IORQ) pin, which is the pin used by the Z80 to tell the I/O chip that it needs to access I/O.

No I/O address decoding is done, which mean your single 6522 hogs the entire I/O address space. No other I/O device can be added to the bus, else you'll have a data bus conflict.
This is what chip select lines are for. He hard-wires the two CS lines (one high, the other low) to keep the single 6522 awake. If you want two 6522s on the bus, connect one of the CS lines (of each 6522) to a Z80 address line to select one or the other. And thanks for the memories.

Answer 3

I don't quite understand the idea of I/O ports.

I/O ports are like memory locations, except /IOREQ is used to select them rather than /MREQ. On the Z80 an I/O instruction such as OUT (0xFF),A or IN A,(0xFF) puts the 8 bit address 0xFF on the lower 8 address lines, then pulses /IOREQ low to select the I/O chip. This provides an I/O space with 256 locations. The Z80 can also have a 16 bit I/O space using instructions such as OUT (C),A, which puts the contents of the B register onto the upper 8 bits of the address bus.

To have multiple I/O chips on the same bus each one must be selected at a different address. For chips which only have one select line you can wire each one to a different address line and then address up to 8 chips with 8 bit I/O instructions, eg. first chip selected when A0 is low and all others high, second when A1 is low etc. With this method you must not use any address which has both A0 and A1 low or both chips would be selected at the same time, causing a bus conflict.

This is called 'partial' address decoding, which was used in many home computers such as the Sinclair ZX Spectrum and Amstrad CPC. Other computers with CPUs that have no I/O space (eg. 6502) have to address their I/O chips in memory space, and therefore usually do more complete address decoding because otherwise it would waste too much memory space.