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I'm looking to take the output of some registers (e.g. 74LS670) and have them each be able to output either to an A bus or a B bus, obviously only one register can output on each bus at one time. I've looked at decoders/demultiplexers, multiplexers, etc and either I'm not finding what I need, or I'm too ignorant to see my use case in the various data sheets I've read through. I'm basically needing a SPDT switch that can be controlled by another logic signal. I'm trying to stick with the 74LS series if possible, or at the very least I need something TTL compatible. Any help is definitely appreciated.

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    \$\begingroup\$ The straightforward way is to use an additional 74LS244. \$\endgroup\$
    – Janka
    Nov 10, 2017 at 0:27

3 Answers 3

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You need to use a tristate buffer, such as a 74LS125. Use two inputs on each output from your register. This allows you to put an output into high impedance state (high Z), so it will not affect the bus when it's in that state. You then need control logic which determines which (if any) register drives the buses at any one time.

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  • \$\begingroup\$ How is that brute force? That's 100% okay. \$\endgroup\$ Nov 10, 2017 at 0:40
  • \$\begingroup\$ Just in terms of IC choice. I suspect there's a more compact (e.g. all 4 bits controlled by a single line) IC out there. The approach itself is not brute force; changed answer accordingly @HarrySvensson :) \$\endgroup\$
    – awjlogan
    Nov 10, 2017 at 0:44
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The 74LS670 is a 4x4 Reg. with dual access for R/W and a separate Wg_ write enable port from tristate where both active high and low drivers are disabled and any other port can then use the bus. Using an address decoder chip can be use to select 1 of 4, 8 or 16 ports with 2,3 or 4 address bits. For 2 ports you can consider using the inverse of 1 signal but there may be a glitch on the Vcc during the transition time so it is often gated with the inverse clock so that address changes occur before the bus is enabled. enter image description here

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Consider using two 74670's wired so their data input and write addressing is wired in common so they act like a single register for write, but then wire the outputs so that one chip goes to bus A and the other to bus B.

You end up with a three port x 4 bit device with independent addressing as:

  • 2 bits address controlling which of the 4 locations get written to

  • 2 bits address controlling which of the 4 locations is asserted on bus A

  • 2 bits address controlling which of the 4 locations is asserted on bus B

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