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In his book "Modern Operating Systems", Tanenbaum makes a statement about processors speed that I can't understand:

According to Einstein’s special theory of relativity, no electrical signal can propagate faster than the speed of light, which is about 30 cm/nsec in vacuum and about 20 cm/nsec in copper wire or optical fiber. This means that in a computer with a 10-GHz clock, the signals cannot travel more than 2 cm in total. For a 100-GHz computer the total path length is at most 2 mm. A 1-THz (1000-GHz) computer will have to be smaller than 100 microns, just to let the signal get from one end to the other and back once within a single clock cycle.

I am aware that the speed of an electromagnetial perturbation is not the same in different environments, so it is easy to grasp that the speed of light "is about 30 cm/nsec in vacuum and about 20 cm/nsec in copper wire or optical fiber". However, how it is possible to infer that signals traveling inside a 10-GHz CPU cannot travel more than 2 cm? Is that related somehow to the wavelength of a 10 GHz signal that is traveling at 20 cm/nsec? If it is related, how to conclude that an 1-THz CPU would have to be smaller than 100 microns, once the wavelength of an 1-THz signal is 200 microns?

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    \$\begingroup\$ They can travel more than 2cm, but it will take more than 1 clock cycle for them to do so \$\endgroup\$ – BeB00 Nov 10 '17 at 18:15
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The limit he gives is predicated on an assumption of the entire chip being in a single clock domain. Large chips have used multiple clock domains for years though.

From a practical perspective, frequency limits on high-end CPUs mostly depend on the ability to deliver and dissipate power. With sufficient cooling, overclockers routinely exceed the specified limits on CPU speed by substantial margins.

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  • \$\begingroup\$ You used an expression that made a ring bell: "clock domain". But Tanenbaum also states that, for a hypothetical 1-THz rate, the CPU have to be smaller than 100 microns in order to "let the signal get from one end to the other and back within a single clock cycle". Why is it important to make distances short enough to allow signals go back and forth within a single clock cycle? It doesn't make any sense to me since (as far as I understand) the important thing here is to send a signal within a single clock cycle, not send and receive a signal. Can you clarify that, please? \$\endgroup\$ – Humberto Fioravante Ferro Nov 13 '17 at 14:01
  • \$\begingroup\$ @HumbertoFioravanteFerro: It depends. Multiple clocks to write a value can be perfectly acceptable. Multiple clocks to read from a register would generally be considered a lot less acceptable. \$\endgroup\$ – Jerry Coffin Nov 13 '17 at 14:26
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The chip itself can be any size (within tech limits), but propagation time is an issue already. Very big chips such as high cell count FPGAs frequently have multiple clock sources, so the local propagation distance can be made small. Synthesis and route/place tools will warn of timing violations, and the propagation time is part of that calculation. You then have to consider changing your design, or treating your component in multiple clock domains, with signals that go between domains being resynchronised (if they are clocked).

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