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I have trouble understanding conversion between different data types in VHDL and needed help with conversion to `STD_LOGIC_VECTOR' type in VHDL.

I want the code below to be synthesized such that it can be used on real hardware.

For now i have the code setup as follows

signal   VREF  : real := 65536/3.3;
constant SIG   : real := 2.33;
signal TEMP    : unsigned(15 downto 0);

signal WORD_A : STD_LOGIC_VECTOR(23 downto 0) ;
signal SIG_A  : STD_LOGIC_VECTOR(15 downto 0);

BEGIN

TEMP <= to_unsigned(VREF,16)*to_unsigned(SIG,16);
SIG_A <= STD_LOGIC_VECTOR(TEMP);
WORD_A <= "00110000" & SIG_A;

I used the following libraries : IEEE_NUMERIC_STD.ALL, IEEE.MATH.REAL

I get the following error ERROR: [VRFC 10-1471] type error near VREF ; current type real; expected type natural

Any inputs is appreciated

Thanks

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  • 2
    \$\begingroup\$ You probably want to use the (VHDL-2008) IEEE fixed or floating point packages rather than real, because they are synthesisable. \$\endgroup\$ – Brian Drummond Nov 11 '17 at 0:10
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real is not synthesisable in FPGA. You can use:

library ieee

package ieee_fixed_pkg.all

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This code compiles :

LIBRARY  ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY TEST IS

END ENTITY TEST;

ARCHITECTURE BEH OF TEST is
  signal   VREF  : real := 65536.0 /3.3;
  constant SIG   : real := 2.33;
  signal TEMP    : unsigned(31 DOWNTO 0);

  signal WORD_A : STD_LOGIC_VECTOR(23 DOWNTO 0);
  signal SIG_A  : STD_LOGIC_VECTOR(15 DOWNTO 0);

BEGIN
  TEMP <= to_unsigned(natural(VREF),16)*to_unsigned(natural(SIG),16);
  SIG_A <= STD_LOGIC_VECTOR(TEMP(15 DOWNTO 0));
  WORD_A <= "00110000" & SIG_A;
END ARCHITECTURE BEH;

Note the natural() type cast, because reals cannot be directly converted to unsigned using only basic IEEE libraries.

The "real" type is not synthesisable: you cannot synthesize signals of type real, BUT you can calculate constants using reals and convert them to integers in synthesisable code.

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  • \$\begingroup\$ Thanks @TEMLIB The code does compile, but on the testbench fails to run. I am still confused how VHDL datatypes work on real numbers. Wont converting real to integers result in loss of precision? Thanks \$\endgroup\$ – CanisMajoris Nov 13 '17 at 15:21

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