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I am doing a design in vhdl for FPGA. I have a top level design which consists of 3 components: clock divider, Module_1 and Module_2. Top level entity has a clock input port. This clock is divided by the clock divider to get two other clocks: clock_1 and clock_2. They are fed to Module_1 and Module_2 's clock ports respectively.

I want to constraint all these clocks. So, how to decide whether get_ports or get_pins or get_nets or get_registers have to be used? I used get_ports for the main clock. What about the other two? I can see these generated clocks under get_pins and get_nets and get_registers in the timing analyser of Quartus II. Also the clock names look different in there with some suffixes like '_var' , '~clk' etc. Are there any specific rules for get_pins and get_nets and get_registers ?

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I/Os of the top-level block are called port, I/Os of the subblocks are called pin. So get_ports and get_pins commands must be used accordingly.

If the main clock is an input of the top-level block, get_ports is the appropriate command. For example:

create_clock -name CLK [get_ports clock_main] ...

Since clock_1 and clock_2 are the inputs of the subblocks, get_pins must be used in this case.

create_clock -name CLK1 [get_pins Module_1/clock_1] ...
create_clock -name CLK2 [get_pins Module_2/clock_2] ...

The signals other than the I/Os are called net. The nets may be collected and constrained by using get_nets command, however most of the synthesis tools optimize out them or change the names. It is better to avoid using get_nets if not mandatory. Otherwise most of the synthesis tools require dont_touch attribute or something similar to keep the net.

Normally I don't use get_registers command, because it's not supported by Synopsys Design Compiler, I use get_cells instead. On the contrary, Quartus II supports get_registers according to Altera's SDC manual.

It can be also used to constrain the clock. The manual has the following example:

create_generated_clock -divide_by 2 -source [get_ports clk] -name clkdiv \
  [get_registers clkdiv]

Alternatively you may use get_pins command. It's up to you.

create_generated_clock -divide_by 2 -source [get_ports clk] -name clkdiv \
  [get_pins clkdiv/Q]

If you have such a clock divider in your design, it's better to constrain it on the register or Q pin than the clock input of a subblock (e.g. Module_1). Otherwise the synthesis tool doesn't know whether the path carries a clock signal between the register and the clock_1 pin. The delay of the path is not included in the timing analysis etc.

Synthesis tools commonly add suffixes to the signal and cell names. Each tool has its own naming rules. For example, my tool adds _reg suffix to the flopped signals.

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  • \$\begingroup\$ You mean its better to constraint the output Q pin of the clock divider module (get_register) rather than the input pin (get_pin) of module_1 ? \$\endgroup\$ – Mitu Raj Nov 15 '17 at 12:16
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    \$\begingroup\$ @MITURAJ Yes. There is one more advantage. If you connect the same divided clock to a third subblock (e.g. Module_3) later, you will not need to add a new constraint for that. A constraint on Q pin propagates to all sinks of that clock. \$\endgroup\$ – ahmedus Nov 15 '17 at 12:33
  • \$\begingroup\$ Oh yea !! Great point. Was looking for this answer for long time. Cheers bro 👍 \$\endgroup\$ – Mitu Raj Nov 15 '17 at 12:35

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