# Design circuit with least logic gates

As part of an exercise, i have 4 inputs and 3 outputs F1,F2,F3. After minimizing with Karnaugh maps one of the inputs is eliminated and i get these 3 outputs:

F1= x'y'z'
F2= x'y z'+ x z
F3= x'z +x y + x y'z'

Can i make this any simpler or can i start implementing it with Logic gates? I want to use AND, OR, NOT gates of 2 inputs only and right now i am able to do it with about 15 gates.

• Looks like 3 inputs 3 outputs; you can reduce 1 gate i.e. x' & z' use it in F1 and F2 ; or y' & z' use it both F1 and F3 – rsg1710 Nov 12 '17 at 19:16

$F3= \bar xz +x y + x \bar y \bar z$
$F3= \bar xz +x y (1 + \bar z) + x \bar y \bar z$
$F3= \bar xz + x y + x y\bar z + x \bar y \bar z$
$F3= \bar xz + x y + x\bar z (y + \bar y)$
$F3= \bar xz + x y + x\bar z$