# Is the FET gate resistance counted on the RC time constant?

As I understand, a logic "1" output to an input of another IC can be modeled like this :

simulate this circuit – Schematic created using CircuitLab

with C1 representing output capacitance, R1 the Rds(on) of the internal FETs of the "emitter" IC, C2 representing the input capacitance, and R2 representing the resistance at the gate of the "receiving" chip. (all values are sample values from a few datasheets; R2 is extrapolated conservatively.)

But, when trying to calculate the time for the gate to receive the "1" (which I supposed to be the instant at which the voltage across C2 is equal to the threshold voltage, as, if it were based on the voltage across R2, it would be immediate, and I know that the RC time constant does cause problems at high speeds, so it can't be that.) (R1 is not taken into account to facilitate calculations)

$$ESC = (\frac 2 5 * 10^{12} + \frac 2 7 * 10^{12})^{-1} = 1.25*10^{-12} F$$ $$\tau = 1.0*10^7 * 1.25*10^{-12} = 1.25*10^{-5} s$$ $$Q(t) = 1.25*10^{-12} * 5(1 - e^{{-t} / \tau})$$ or : $V = \frac Q C$ so, solving this equation for t should do : $$3.5 = \frac {Q(t)} {2.5 * 10^{-12}}$$ $$\Rightarrow 3.5 = \frac {1.25*10^{-12} * 5(1 - e^{{-t} / ({1.25*10^{-5}})})} {2.5 * 10^{-12}}$$ $$\Rightarrow 3.5 = \frac {1.25 * 5(1 - e^{{-t} / ({1.25*10^{-5}})})} {2.5}$$

$$\Rightarrow 3.5 = \frac {5(1 - e^{{-t} / ({1.25*10^{-5}})})} {2}$$

$$\Rightarrow 7 = 5(1 - e^{{-t} / ({1.25*10^{-5}})})$$

$$\Rightarrow 2 = -5 * e^{-t / ({1.25*10^{-5}})}$$ $$\Rightarrow \frac 2 5 = -e^{-t / ({1.25*10^{-5}})}$$ $$\Rightarrow \ln (\frac 2 5) = -\frac {-t} {1.25*10^{-5}}$$ $$\Rightarrow -1 * \ln(\frac 2 5) * 1.25*10^{-5} = -t$$ $$\Rightarrow t \approx -0.00001145363 s$$

But that is obviously wrong. If the "typical" propagation of the signal between ICs, why make ICs who have propagations times in the nanoseconds, as the carrying of the signal is far more restraining than the actual "compute" time ?

I'm sure I've made a mistake somewhere, maybe in my assumptions, certainly in my equations, the result being negative. What is it ? And what is the correct way to think about input/output capacitance ? I think it has to do with the FET's gate resistance, but I'm not sure...

Your model doesn't make a lot of sense. You probably want something more like this

simulate this circuit – Schematic created using CircuitLab

The buffers here represent ideal devices, with the non-idealities modeled by the R and C elements.

Notice in particular the capacitors are not in series with the signal path.

I'd also say that your capacitance values seem quite high. Values in the 5-10 picofarad range are more common, even for discrete logic ICs. Consult the datasheets for the parts you want to model to get reasonable values.

• Thank you for your answer ! The uF values are a mistake of the diagram, I thought I had put pF instead of uF. I used the typical values from this datasheet – Sachiko.Shinozaki Nov 13 '17 at 0:39
• So, if I understand your model correctly, here : $$\tau = 10 * \frac 1 {1/C_{out} + 1/C_{in}}$$ – Sachiko.Shinozaki Nov 13 '17 at 0:44
• Recheck your formula for combining capacitors in parallel. – The Photon Nov 13 '17 at 0:46
• I must be really tired... $$\tau = 10 * (C_{in} + C_{out})$$ But then, I wonder, how does the ideal buffer draw so little when it's resistance is in parallel to it ? – Sachiko.Shinozaki Nov 13 '17 at 0:49
• 1 megohm is an underestimate of the input resistance of a CMOS gate. Gigohms are possible (in which case, PCB parasitics may be more important to model). – The Photon Nov 13 '17 at 0:51