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I'm looking over the following question:

enter image description here

I have the answer, and for the most part, I think I understand the logic: y = z' and z = xy. There's a 15ns delay (10 from the AND gate and 5 from the inverter) when coming back around to z. But my question has to do with Z on the timing diagram:

enter image description here

First, how do we know when Z starts? It looks like it goes from 0 to 1 10 ns after x does, but why? Is that all there is to it? Also, what is determining when z goes from 0 to 1 (with the 15 ns delay, I guess)? I really hope my questions make sense and that someone can clarify what is going on in the diagram for me -- I'm sure I've overlooked something in the circuit.

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  • \$\begingroup\$ Try again... When x=0 what is Z? \$\endgroup\$ – Sunnyskyguy EE75 Nov 13 '17 at 4:40
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    \$\begingroup\$ @TonyStewart.EEsince'75 If x = 0, since xy uses an AND gate, would that make z = 0? \$\endgroup\$ – gbm0102 Nov 13 '17 at 4:54
  • \$\begingroup\$ correct........ \$\endgroup\$ – Sunnyskyguy EE75 Nov 13 '17 at 5:20
  • \$\begingroup\$ But x is 1 for for quite a while, and z rises and falls between then -- that was my second question. What is causing z to rise and fall? \$\endgroup\$ – gbm0102 Nov 13 '17 at 5:45
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    \$\begingroup\$ When 'x' is "0" the AND gate is disabled and the output of the AND gate is forced to "0" without respect to 'y'. So that's stable. But when 'x' is "1" the AND gate is enabled so that the value at 'y' is copied to 'z'. Because there is an inverter in that path, 'z' toggles back and forth as 'z' is inverted to 'y' and then 'y' is copied to 'z' and then 'z' is inverted to 'y' and ... The way to shut that down again is to set 'x' to "0" and disable the AND gate, again. \$\endgroup\$ – jonk Nov 13 '17 at 6:28

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