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I am new to eagle Software and designing few development boards. When I finish my design and check for DRC Errors, I get lot of Dimension and overlap Errors. Components like spark fun SMD Crystal has many Dimension Errors and I am not getting rid of them.

I have also checked the DRC Errors in eagle examples like MSP430F5529 launchpad. The layout has got DRC Errors by default.

My doubt is whether I should take these Errors seriously or should I just give the generated gerber files to the fabrication!

I have attached the Screen shot showing DRC Errors to Crystal I was talking about.

Another Picture showing width error which I am not able to understand

This is a Picture representing small gnd to gnd Routing. Even this is showing a width error. Am I Routing wrong between different components?

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    \$\begingroup\$ Please add a screenshot showing one or more errors, and the corresponding error message. \$\endgroup\$ – pipe Nov 13 '17 at 12:33
  • \$\begingroup\$ Added Screen shots of Errors which I am not able to understand. \$\endgroup\$ – code_slack Nov 13 '17 at 13:07
  • \$\begingroup\$ In the crystal example, open the footprint and see if there is anything drawn on the "dimension" layer. If there is, delete it, whoever made the footprint did it wrong. \$\endgroup\$ – Tom Carpenter Nov 13 '17 at 13:09
  • \$\begingroup\$ "Width Error" means the trace width is too narrow. Make the traces larger... \$\endgroup\$ – Tom Carpenter Nov 13 '17 at 13:10
  • \$\begingroup\$ "Overlap" error means that two traces on different nets are shorted out. \$\endgroup\$ – Tom Carpenter Nov 13 '17 at 13:11
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Yes, these are almost always serious, at least if you don't know why they occur.

My guess is that you have not changed your design rules according to your manufacturer but left them as default. For example, the default may have a 12 mil clearance limit while you are using tiny SMD circuits which requires an 8 mil clearance.

If you get actual overlap errors, then you may have drawn traces on top of other traces. Hard to tell without a screenshot and a list of errors.

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  • \$\begingroup\$ Added a Screen shot of width and Dimension error which I did not understand \$\endgroup\$ – code_slack Nov 13 '17 at 12:44
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Yea very important. DRC rules are set of design rules regarding widths, spacing etc., specified by the fab. These rules set the minimum requirement to avoid the failure of your circuit due to fabrication faults.

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  • \$\begingroup\$ How could I avoid the width error in the N$10 net as shown in the Fig2? \$\endgroup\$ – code_slack Nov 13 '17 at 12:59
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It is a matter of sticking to standards, depending on the design requirements the design rules have to be setup and ideally all conflicting parts/connections should be checked and rectified. The design rules can be set easily on eagle and there are downloadable design rules for Sparkfun etc. If it is a simple board by all means check conflicting rules visually and override them but for complex designs spanning over 4 or more layers this may be difficult to ascertain.

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Notice the pad gap is less than track width. You can easily move via position with pin 1 track to fix this gap issue in 1st case and same in 2nd case.

other info

Usually smallest track width equals smallest gap becuase Minimum gap width affects cost of board from some sources.. 8mil vs 5 vs 3...

Some people prefer teardrop pads to make the pad-track edge stronger, which depends on quality of board.

Some shops also do free DRC, which is critical in any design. So fix it now.

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