I need advise about LIN bus ESD protection. Here a four LIN connectors on board but only one LIN driver (master), is it mean that ESD protective diodes also must be 4? placed close to each connection? And take into account capacitance of these four ESD diodes?
1\$\begingroup\$ I couldn't understand how the system is. Maybe a scheme would be quite helpful. ESD diodes' capacitances are not that important, because LIN is a low-speed system (You know that it is UART based). \$\endgroup\$– Rohat KılıçNov 13, 2017 at 14:44
I would strongly recommend putting an ESD diode on the LIN line near each connector. The reason is that you don't want the ESD currents to flow into your PCB where they may couple into unprotected internal tracks. This can cause no end of confusing issues that can be extremely hard to track down. If you just shunt the ESD pulse away at the connector, you keep the high voltages and currents away from the rest of your system.
On a low speed bus like LIN the extra capacitance is not going to be an issue, so I can't really see why you wouldn't do this unless cost was an extreme issue. If that is true, you can always put footprints for five TVS diode clamps on the board and then verify on the final hardware exactly what is required.
\$\begingroup\$ Thank you for advise, yes I'm agree ESD diodes must be placed at each connector, and I was worry about capasitance of these diodes, but after reading nxp.com/docs/en/application-note/AN00093.pdf I found that Cmaster has take into account number of LIN slaves, bus length and so on... finaly it becomes in nano farad order - which compare to diodes 17pF capasitance is nothing \$\endgroup\$ Nov 14, 2017 at 4:18
I think you might benefit from a better understanding of ESD. If you understand it it becomes clear what needs to be done.
ESD is a pulse-like electrical discharge onto a conductor.
A bad ESD pulse can be 4 Amps or more.
ICs are rated and tested to handle a certain ESD level, for example 2 kV HBM (Human Body Model).
ESD does not distinguish between inputs and outputs.
ESD can damage sensitive components.
You only need to protect the conductors that are connected to a point which can get an ESD pulse. So internal lines on a PCB: no protection needed. Connector on your product: all pins need ESD protection.
So I would add protection diodes to all 4 lines.
I do not think the capacitance will be an issue since the LIN Bus uses quite low frequency signals. The capacitance of the wires (the bus) will be much more than the capacitance added by the protection diodes.
\$\begingroup\$ Why do all you IC manufacturers still spec everything relative to HBM? Nobody that cares tests that way. \$\endgroup\$ Nov 13, 2017 at 14:58
1\$\begingroup\$ @MattYoung Nobody that cares tests that way. Maybe not in your world/environment. I'm at the IC design side and our customers expect HBM model based levels. There is indeed also CDM (Charged device model) and MM (Machine model) which can be tougher to meet. I guess that HBM is still there for historic reasons. \$\endgroup\$ Nov 13, 2017 at 15:05
\$\begingroup\$ All I know is that 2kV HBM spec has been in almost every IC datasheet I've ever seen. On the other hand, almost every protection device has been spec'd to IEC61000-4-2, which actually makes sense, since that's the only standard you ever hear people system testing against. Some of the things that are normal in this industry are funny... \$\endgroup\$ Nov 13, 2017 at 15:14
ESD protection is a sub-nanosecond clamp, so it needs to be close to IC. If there is inductance between clamp and IC then the clamp diode sees a delayed pulse and is less effective. We call this a low ESL connection, like low ESR but for inductance.(L)
ESD rise time of ionization between a key held by hand and connector or simply connecting a loose charged cable, can be as small as few picoseconds with some charge voltage. So low ESL is important for clamp protection and series R for current limiting. So result looks like pulse with ringing somewhat like standard lightning test but much lower (nano) Coulombs but much faster rise time due to smaller gap. (<1ns vs ~1us)
So if discharge is say 1A in 100 ps rise time and ESL is 100nH what is voltage rise on conductor path? V=LdI/dt
What does it need to need to prevent CMOS Latchup?
ESD actually has low negative resistance (ESR) and conductor interface has positive ESR, so effect on clamp voltage rise with any discharge results in rapid discharge of small C into series RL then diode then path to IC input pin must not exceed rails by +0.3V. as far as I recall...
Now you should be able to answer your own question.
\$\begingroup\$ I guess those who voted -1 have no expertise in this area and should not vote until they appreciate experience. If you understand inductance, the simple answer is Yes for each port. \$\endgroup\$ Nov 14, 2017 at 17:52